diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv
index a82f4e9bf..d6e6a75e4 100644
--- a/src/ifu/spill.sv
+++ b/src/ifu/spill.sv
@@ -83,6 +83,7 @@ module spill import cvw::*;  #(parameter cvw_t P) (
     assign SpillF = CacheableF ? SpillCachedF : SpillUncachedF;
   end else
     assign SpillF = PCF[1]; // *** might relax - only spill if next instruction is uncompressed
+  // Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
   assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF));
   
   always_ff @(posedge clk)
diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv
index 666448b12..31312f767 100644
--- a/src/mmu/tlb/tlbcontrol.sv
+++ b/src/mmu/tlb/tlbcontrol.sv
@@ -115,8 +115,7 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   end
 
   // Determine wheter to update DA bits.  With SVADU, it is done in hardware
-  if (P.SVADU_SUPPORTED) assign UpdateDA = PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE;
-  else                   assign UpdateDA = PreUpdateDA;
+  assign UpdateDA = P.SVADU_SUPPORTED & PreUpdateDA & Translate & TLBHit & ~TLBPageFault & ENVCFG_HADE;
 
   // Determine whether page fault occurs
   assign PrePageFault = UpperBitsUnequal | Misaligned | ~PTE_V | ImproperPrivilege | (P.XLEN == 64 & (BadPBMT | BadNAPOT | BadReserved)) | (PreUpdateDA & (~P.SVADU_SUPPORTED | ~ENVCFG_HADE));