From 19096a812adb9e100d98fb1abf1810ab741c77fa Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Tue, 16 May 2023 11:18:27 -0700
Subject: [PATCH] Added Zifencei ISA to tests where necessary to support new
 compiler

---
 setup.sh                                                        | 1 +
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S     | 2 +-
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S      | 2 +-
 .../rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S             | 2 +-
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S      | 2 +-
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S    | 2 +-
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S       | 2 +-
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S       | 2 +-
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S      | 2 +-
 .../rv32i_m/privilege/src/WALLY-uart-timeout-01.S               | 2 +-
 .../riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S     | 2 +-
 .../riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S      | 2 +-
 .../rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S             | 2 +-
 .../rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S             | 2 +-
 .../riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S      | 2 +-
 .../riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S    | 2 +-
 .../riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S       | 2 +-
 .../riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S       | 2 +-
 .../riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S      | 2 +-
 19 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/setup.sh b/setup.sh
index 2115a0d71..95026beb1 100755
--- a/setup.sh
+++ b/setup.sh
@@ -17,6 +17,7 @@ echo \$WALLY set to ${WALLY}
 export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu                   # Change this to your Siemens license server
 export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server
 export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_2/questasim        # Change this for your path to Questa, excluding bin
+#export QUESTA_HOME=/cad/mentor/questa_sim-2022.4_3/questasim        # Change this for your path to Questa, excluding bin
 export SNPS_HOME=/cad/synopsys/SYN                                  # Change this for your path to Design Compiler, excluding bin
 
 # Path to RISC-V Tools
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
index f04a51d50..b0ad29128 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-32.h" 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) 
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
index 0bcce74b5..94021491d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
index a71ab485c..f864d255c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True; def NO_SAIL=True;",mmu)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
index c728f5721..038b9ce00 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
index 80204cf1c..f48771c5e 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
index ceba7374c..0c1c7bbb2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma-01.S
@@ -36,7 +36,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
index a37e95365..4daddb3fb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
index c18ed2629..101154923 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
index 106580b88..2ed238e23 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-32.h" 
 
-RVTEST_ISA("RV32I_Zicsr")
+RVTEST_ISA("RV32I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart-timeout)
 
 .equ UART, 0x10000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
index 838e4654d..3aaa58706 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-clint-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) 
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
index 3782ea561..c991721ea 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-gpio-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S
index 68c77a1aa..80df44a1a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",mmu-sv39)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
index bcb93d670..9b8925fb5 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",sv48)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
index 0056c9c72..ce15c0525 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
index 68161276c..3f312c9b3 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S
@@ -24,7 +24,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
index e340302e5..a5385e001 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma-01.S
@@ -35,7 +35,7 @@
 #define PLIC_RANGE     0x03FFFFFF
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
index e8da53c3a..140c0d97d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S
@@ -22,7 +22,7 @@
 ///////////////////////////////////////////
 
 #include "WALLY-TEST-LIB-64.h" 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp)
 
 INIT_TESTS
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
index 32423d247..2c2b2ab07 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-uart-01.S
@@ -23,7 +23,7 @@
 
 #include "WALLY-TEST-LIB-64.h" 
 
-RVTEST_ISA("RV64I_Zicsr")
+RVTEST_ISA("RV64I_Zicsr_Zifencei")
 RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart)
 
 INIT_TESTS