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Got the shadow ram cache flush working.

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This commit is contained in:
Ross Thompson 2021-07-13 10:03:47 -05:00
parent 9fe6190763
commit 17dc488010
2 changed files with 19 additions and 9 deletions
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9
wally-pipelined/regression/wave.do
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@ -402,19 +402,22 @@ add wave -noupdate /testbench/dut/uncore/dtim/RAM
add wave -noupdate /testbench/dut/uncore/dtim/A add wave -noupdate /testbench/dut/uncore/dtim/A
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate /testbench/dut/uncore/dtim/memwrite
add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
add wave -noupdate /testbench/dut/uncore/dtim/memread add wave -noupdate /testbench/dut/uncore/dtim/memread
add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
add wave -noupdate /testbench/dut/uncore/dtim/HCLK add wave -noupdate /testbench/dut/uncore/dtim/HCLK
add wave -noupdate /testbench/dut/hart/clk add wave -noupdate /testbench/dut/hart/clk
add wave -noupdate /testbench/DCacheFlushFSM/CacheData add wave -noupdate /testbench/DCacheFlushFSM/CacheData
add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM
add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr
add wave -noupdate /testbench/DCacheFlushFSM/CacheData add wave -noupdate /testbench/DCacheFlushFSM/CacheData
add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty
add wave -noupdate /testbench/DCacheFlushFSM/CacheTag add wave -noupdate /testbench/DCacheFlushFSM/CacheTag
add wave -noupdate /testbench/DCacheFlushFSM/CacheValid add wave -noupdate /testbench/DCacheFlushFSM/CacheValid
add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/clk
add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/start
add wave -noupdate -expand -group shadowram -color Orchid /testbench/DCacheFlushFSM/ShadowRAM
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 12} {63874 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0} WaveRestoreCursors {{Cursor 12} {63589 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0}
quietly wave cursor active 1 quietly wave cursor active 1
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 297 configure wave -valuecolwidth 297
@ -430,4 +433,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ns} {67394 ns} WaveRestoreZoom {63529 ns} {63661 ns}

13
wally-pipelined/testbench/testbench-imperas.sv
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@ -630,11 +630,14 @@ string tests32f[] = '{
// check results // check results
always @(negedge clk) always @(negedge clk)
begin begin
/* -----\/----- EXCLUDED -----\/-----
if (dut.hart.priv.EcallFaultM && if (dut.hart.priv.EcallFaultM &&
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.hart.ieu.dp.regf.we3 && (dut.hart.ieu.dp.regf.we3 &&
dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.a3 == 3 &&
dut.hart.ieu.dp.regf.wd3 == 1))) begin dut.hart.ieu.dp.regf.wd3 == 1))) begin
-----/\----- EXCLUDED -----/\----- */
if (DCacheFlushDone) begin
$display("Code ended with ecall with gp = 1"); $display("Code ended with ecall with gp = 1");
#600; // give time for instructions in pipeline to finish #600; // give time for instructions in pipeline to finish
@ -1035,9 +1038,10 @@ module DCacheFlushFSM
if (start) begin #1 if (start) begin #1
for(i = 0; i < numlines; i++) begin for(i = 0; i < numlines; i++) begin
for(j = 0; j < numways; j++) begin for(j = 0; j < numways; j++) begin
for(k = 0; k < numwords; k++) begin if (CacheValid[j][i] && CacheDirty[j][i]) begin
$display("Help me!") for(k = 0; k < numwords; k++) begin
ShadowRAM[CacheAdr[j][i][k]] = CacheData[j][i][k]; ShadowRAM[CacheAdr[j][i][k]/8] = CacheData[j][i][k];
end
end end
end end
end end
@ -1045,6 +1049,9 @@ module DCacheFlushFSM
end end
flop #(1) doneReg(.clk(clk),
.d(start),
.q(done));
endmodule endmodule