From 17dc488010ab494bcaf6784685d228db7ac3d946 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Tue, 13 Jul 2021 10:03:47 -0500
Subject: [PATCH] Got the shadow ram cache flush working.

---
 wally-pipelined/regression/wave.do            |  9 ++++++---
 .../testbench/testbench-imperas.sv            | 19 +++++++++++++------
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index b2b477ba9..753e51958 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -402,19 +402,22 @@ add wave -noupdate /testbench/dut/uncore/dtim/RAM
 add wave -noupdate /testbench/dut/uncore/dtim/A
 add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
 add wave -noupdate /testbench/dut/uncore/dtim/memwrite
+add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
 add wave -noupdate /testbench/dut/uncore/dtim/memread
 add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
 add wave -noupdate /testbench/dut/uncore/dtim/HCLK
 add wave -noupdate /testbench/dut/hart/clk
 add wave -noupdate /testbench/DCacheFlushFSM/CacheData
-add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM
 add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr
 add wave -noupdate /testbench/DCacheFlushFSM/CacheData
 add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty
 add wave -noupdate /testbench/DCacheFlushFSM/CacheTag
 add wave -noupdate /testbench/DCacheFlushFSM/CacheValid
+add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/clk
+add wave -noupdate -expand -group shadowram /testbench/DCacheFlushFSM/start
+add wave -noupdate -expand -group shadowram -color Orchid /testbench/DCacheFlushFSM/ShadowRAM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 12} {63874 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0}
+WaveRestoreCursors {{Cursor 12} {63589 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
@@ -430,4 +433,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ns} {67394 ns}
+WaveRestoreZoom {63529 ns} {63661 ns}
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index b9b145581..fa43c560a 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -630,11 +630,14 @@ string tests32f[] = '{
   // check results
   always @(negedge clk)
     begin    
+/* -----\/----- EXCLUDED -----\/-----
       if (dut.hart.priv.EcallFaultM && 
 			    (dut.hart.ieu.dp.regf.rf[3] == 1 || 
 			     (dut.hart.ieu.dp.regf.we3 && 
 			      dut.hart.ieu.dp.regf.a3 == 3 && 
 			      dut.hart.ieu.dp.regf.wd3 == 1))) begin
+ -----/\----- EXCLUDED -----/\----- */
+      if (DCacheFlushDone) begin
         $display("Code ended with ecall with gp = 1");
 
         #600; // give time for instructions in pipeline to finish
@@ -1035,16 +1038,20 @@ module DCacheFlushFSM
     if (start) begin #1
       for(i = 0; i < numlines; i++) begin
 	for(j = 0; j < numways; j++) begin
-	  for(k = 0; k < numwords; k++) begin
-	    $display("Help me!")
-	    ShadowRAM[CacheAdr[j][i][k]] = CacheData[j][i][k];
-	  end
+	  if (CacheValid[j][i] && CacheDirty[j][i]) begin
+	    for(k = 0; k < numwords; k++) begin
+	      ShadowRAM[CacheAdr[j][i][k]/8] = CacheData[j][i][k];
+	    end
+	  end	
 	end
       end
     end
   end
-  
-      
+
+
+  flop #(1) doneReg(.clk(clk),
+		    .d(start),
+		    .q(done));
 		    
 endmodule