From 169539f7731770818f0b4189d2c098a0cf94c569 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 31 May 2023 10:02:34 -0500 Subject: [PATCH] Cleanup parameterization for verilator 5.010. --- src/uncore/ram_ahb.sv | 3 ++- src/uncore/rom_ahb.sv | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 1391a5691..b7ec13457 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -28,7 +28,8 @@ `define RAM_LATENCY 0 -module ram_ahb import cvw::*; #(parameter cvw_t P, BASE=0, RANGE = 65535) ( +module ram_ahb import cvw::*; #(parameter cvw_t P, + parameter BASE=0, RANGE = 65535) ( input logic HCLK, HRESETn, input logic HSELRam, input logic [P.PA_BITS-1:0] HADDR, diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index 79a5405e1..abb75277f 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -26,7 +26,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module rom_ahb import cvw::*; #(parameter cvw_t P, BASE=0, RANGE = 65535) ( +module rom_ahb import cvw::*; #(parameter cvw_t P, + parameter BASE=0, RANGE = 65535) ( input logic HCLK, HRESETn, input logic HSELRom, input logic [P.PA_BITS-1:0] HADDR,