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Integrating riscv-dv coverage

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This commit is contained in:
David Harris 2024-04-24 10:17:49 -07:00
parent eb7e5d4bc2
commit 160c11d786
4 changed files with 10 additions and 9 deletions
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4
Makefile
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@ -58,12 +58,12 @@ funcovreg:
vcover report -details -html sim/riscv.ucdb vcover report -details -html sim/riscv.ucdb
# test_name=riscv_arithmetic_basic_test # test_name=riscv_arithmetic_basic_test
rvdv: sim/regression_logs sim/regression_ucdbs rvdv:
python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> sim/regression_logs/${test_name}.log 2>&1 python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> sim/regression_logs/${test_name}.log 2>&1
python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> sim/regression_logs/${test_name}.log 2>&1 python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> sim/regression_logs/${test_name}.log 2>&1
python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> sim/regression_logs/${test_name}.log 2>&1 python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> sim/regression_logs/${test_name}.log 2>&1
# run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1 # run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
/home/qabid/scripts/run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1 run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb
rvdv_regression: rvdv_regression:

4
README.md
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@ -53,10 +53,6 @@ Edit setup.sh and change the following lines to point to the path and license se
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa
export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler
export RISCV_TOOLCHAIN=/opt/riscv # Change this for your path to RISCV GNU toolchain
export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-gcc" # Copy this as it is
export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-objcopy" # Copy this as it is
export SPIKE_PATH=/usr/bin # Change this for your path to riscv-isa-sim (spike)
If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below. If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.

10
site-setup.sh
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@ -11,13 +11,13 @@
# Must edit these based on your local environment. # Must edit these based on your local environment.
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin export QUESTA_HOME=/cad/mentor/questa_sim-2023.4 # Change this for your path to Questa, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin
# Tools # Tools
# Questa and Synopsys # Questa and Synopsys
export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH export PATH=$QUESTA_HOME/questasim/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
# GCC # GCC
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
@ -29,6 +29,11 @@ export PATH=$PATH:$RISCV/bin
# Verilator # Verilator
export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
# environment variables needed for RISCV-DV
export RISCV_GCC=`which riscv64-unknown-elf-gcc` # Copy this as it is
export RISCV_OBJCOPY=`which riscv64-unknown-elf-objcopy` # Copy this as it is
export SPIKE_PATH=/usr/bin # Change this for your path to riscv-isa-sim (spike)
# Imperas OVPsim; put this in if you are using it # Imperas OVPsim; put this in if you are using it
#export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH
#export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH #export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH
@ -44,3 +49,4 @@ if [ -e "$IDV" ]; then
export PATH=$IDV/scripts/cvw:$PATH export PATH=$IDV/scripts/cvw:$PATH
fi fi

1
testbench/testbench-imperas.sv
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@ -324,7 +324,6 @@ module testbench;
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk),
.reset(reset),
.start(DCacheFlushStart), .start(DCacheFlushStart),
.done(DCacheFlushDone)); .done(DCacheFlushDone));