From 160c11d7869c33c6d4c7fe2e8ddbef193a015689 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 24 Apr 2024 10:17:49 -0700
Subject: [PATCH] Integrating riscv-dv coverage

---
 Makefile                       |  4 ++--
 README.md                      |  4 ----
 site-setup.sh                  | 10 ++++++++--
 testbench/testbench-imperas.sv |  1 -
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile
index fab22229d..c96a2e2c6 100644
--- a/Makefile
+++ b/Makefile
@@ -58,12 +58,12 @@ funcovreg:
 	vcover report -details -html sim/riscv.ucdb
 
 # test_name=riscv_arithmetic_basic_test
-rvdv: sim/regression_logs sim/regression_ucdbs
+rvdv: 
 	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen			>> sim/regression_logs/${test_name}.log 2>&1
 	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> sim/regression_logs/${test_name}.log 2>&1
 	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> sim/regression_logs/${test_name}.log 2>&1
 #	run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o													>> sim/regression_logs/${test_name}.log 2>&1
-	/home/qabid/scripts/run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o								>> sim/regression_logs/${test_name}.log 2>&1
+	run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o								>> sim/regression_logs/${test_name}.log 2>&1
 	cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb
 
 rvdv_regression:
diff --git a/README.md b/README.md
index 35c766e91..6379f35a8 100644
--- a/README.md
+++ b/README.md
@@ -53,10 +53,6 @@ Edit setup.sh and change the following lines to point to the path and license se
 	export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                	# Change this to your Synopsys license server
 	export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin     	# Change this for your path to Questa
 	export SNPSPATH=/cad/synopsys/SYN/bin                               	# Change this for your path to Design Compiler
-	export RISCV_TOOLCHAIN=/opt/riscv										# Change this for your path to RISCV GNU toolchain
-	export RISCV_GCC="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-gcc"			# Copy this as it is
-	export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv64-unknown-elf-objcopy"	# Copy this as it is
-	export SPIKE_PATH=/usr/bin												# Change this for your path to riscv-isa-sim (spike)
 
 If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below.
 
diff --git a/site-setup.sh b/site-setup.sh
index 3c15f5e38..a49889a9a 100755
--- a/site-setup.sh
+++ b/site-setup.sh
@@ -11,13 +11,13 @@
 # Must edit these based on your local environment.
 export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu                   # Change this to your Siemens license server for Questa
 export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server for Design Compiler
-export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim          # Change this for your path to Questa, excluding bin
+export QUESTA_HOME=/cad/mentor/questa_sim-2023.4                    # Change this for your path to Questa, excluding bin
 export DC_HOME=/cad/synopsys/SYN                                    # Change this for your path to Synopsys Design Compiler, excluding bin
 export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4                   # Change this for your path to Synopsys VCS, exccluding bin
 
 # Tools
 # Questa and Synopsys
-export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
+export PATH=$QUESTA_HOME/questasim/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
 
 # GCC
 export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
@@ -29,6 +29,11 @@ export PATH=$PATH:$RISCV/bin
 # Verilator
 export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
 
+# environment variables needed for RISCV-DV
+export RISCV_GCC=`which riscv64-unknown-elf-gcc`		            # Copy this as it is
+export RISCV_OBJCOPY=`which riscv64-unknown-elf-objcopy`	        # Copy this as it is
+export SPIKE_PATH=/usr/bin											# Change this for your path to riscv-isa-sim (spike)
+
 # Imperas OVPsim; put this in if you are using it
 #export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH  
 #export LD_LIBRARY_PATH=$RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH
@@ -44,3 +49,4 @@ if [ -e "$IDV" ]; then
     export PATH=$IDV/scripts/cvw:$PATH
 fi
 
+
diff --git a/testbench/testbench-imperas.sv b/testbench/testbench-imperas.sv
index 49f321d00..c315272a6 100644
--- a/testbench/testbench-imperas.sv
+++ b/testbench/testbench-imperas.sv
@@ -324,7 +324,6 @@ module testbench;
            ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" ); 
 
   DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk),
-    			.reset(reset),
 	    		.start(DCacheFlushStart),
 		    	.done(DCacheFlushDone));