diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index dc4d64515..5a07bf55c 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -38,6 +38,7 @@
 `define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
 `define ZCSR_SUPPORTED 1
 `define ZCOUNTERS_SUPPORTED 1
+`define COUNTERS 31
 // N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
 //`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
 `define N_SUPPORTED 0
diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index abd830b80..e9d0621c1 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -106,6 +106,7 @@ module testbench_busybear();
   end
 
   integer warningCount = 0;
+  integer instrs;
 
   //logic[63:0] adrTranslation[4:0];
   //string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"};
@@ -249,6 +250,15 @@ module testbench_busybear();
     end
   end
 
+  always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin
+    if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin
+      $display("!!!!!!illegal (physical) memory access !!!!!!!!!!");
+      $display("(as a reminder, MCAUSE and MEPC are set by this)");
+      $display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR);
+      `ERROR
+    end
+  end
+
   `define CHECK_CSR2(CSR, PATH) \
     string CSR; \
     logic [63:0] expected``CSR``; \
@@ -340,7 +350,6 @@ module testbench_busybear();
   end
 
   string PCtext, PCtext2;
-  integer instrs;
   initial begin
     instrs = 0;
   end