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https://github.com/openhwgroup/cvw
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rename result back to ALUResult in ALU
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@ -37,12 +37,12 @@ module alu #(parameter WIDTH=32) (
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect
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input logic [1:0] CompFlags, // Comparator flags
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output logic [WIDTH-1:0] Result, // ALU result
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output logic [WIDTH-1:0] ALUResult, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, ZBBResult; // Intermediate results
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results
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logic [WIDTH-1:0] MaskB; // BitMask of B
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logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
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logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
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@ -152,8 +152,8 @@ module alu #(parameter WIDTH=32) (
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign ALUResult = FullResult;
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if (WIDTH == 64) assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign CondExtFullResult = FullResult;
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//NOTE: This looks good and can be merged.
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if (`ZBC_SUPPORTED) begin: zbc
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@ -161,7 +161,7 @@ module alu #(parameter WIDTH=32) (
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end else assign ZBCResult = 0;
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if (`ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult));
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zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult));
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end else assign ZBBResult = 0;
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// Final Result B instruction select mux
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@ -169,11 +169,11 @@ module alu #(parameter WIDTH=32) (
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always_comb
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case (BSelect)
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//ZBA_ZBB_ZBC_ZBS
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4'b0001: Result = FullResult;
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4'b0010: Result = ZBCResult;
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4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word.
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4'b0100: Result = ZBBResult;
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default: Result = ALUResult;
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4'b0001: ALUResult = FullResult;
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4'b0010: ALUResult = ZBCResult;
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4'b1000: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word.
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4'b0100: ALUResult = ZBBResult;
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default: ALUResult = CondExtFullResult;
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endcase
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end else assign Result = ALUResult;
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end else assign ALUResult = CondExtFullResult;
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endmodule
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