From 1506d50c63fa528e3193e36a807b655bafcd0188 Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Tue, 28 Feb 2023 07:27:34 -0800
Subject: [PATCH] rename result back to ALUResult in ALU

---
 src/ieu/alu.sv | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
index 96d8c8f52..d5f338276 100644
--- a/src/ieu/alu.sv
+++ b/src/ieu/alu.sv
@@ -37,12 +37,12 @@ module alu #(parameter WIDTH=32) (
   input  logic [2:0]       ZBBSelect,  // ZBB mux select signal
   input  logic [2:0]       Funct3,     // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect
   input  logic [1:0]       CompFlags,  // Comparator flags
-  output logic [WIDTH-1:0] Result,     // ALU result
+  output logic [WIDTH-1:0] ALUResult,     // ALU result
   output logic [WIDTH-1:0] Sum);       // Sum of operands
 
   // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
   // FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
-  logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, ZBBResult; // Intermediate results
+  logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results
   logic [WIDTH-1:0] MaskB;                                                                  // BitMask of B
   logic [WIDTH-1:0] CondMaskB;                                                              // Result of B mask select mux
   logic [WIDTH-1:0] CondShiftA;                                                             // Result of A shifted select mux
@@ -152,8 +152,8 @@ module alu #(parameter WIDTH=32) (
   
 
   // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
-  if (WIDTH == 64)  assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
-  else              assign ALUResult = FullResult;
+  if (WIDTH == 64)  assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
+  else              assign CondExtFullResult = FullResult;
 
   //NOTE: This looks good and can be merged.
   if (`ZBC_SUPPORTED) begin: zbc
@@ -161,7 +161,7 @@ module alu #(parameter WIDTH=32) (
   end else assign ZBCResult = 0;
 
   if (`ZBB_SUPPORTED) begin: zbb
-    zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult));
+    zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult));
   end else assign ZBBResult = 0;
   
   // Final Result B instruction select mux
@@ -169,11 +169,11 @@ module alu #(parameter WIDTH=32) (
     always_comb
       case (BSelect)
       //ZBA_ZBB_ZBC_ZBS
-        4'b0001: Result = FullResult;
-        4'b0010: Result = ZBCResult;
-        4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word.
-        4'b0100: Result = ZBBResult;
-        default: Result = ALUResult;
+        4'b0001: ALUResult = FullResult;
+        4'b0010: ALUResult = ZBCResult;
+        4'b1000: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word.
+        4'b0100: ALUResult = ZBBResult;
+        default: ALUResult = CondExtFullResult;
       endcase
-  end else assign Result = ALUResult;
+  end else assign ALUResult = CondExtFullResult;
 endmodule
\ No newline at end of file