From 1479762ae908743119992202e837e36db7e37805 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 8 Feb 2022 20:15:23 +0000
Subject: [PATCH] RAM simplification

---
 pipelined/src/cache/sram1rw.sv          |  1 +
 pipelined/src/generic/flop/simpleram.sv | 20 ++++++++------------
 2 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/pipelined/src/cache/sram1rw.sv b/pipelined/src/cache/sram1rw.sv
index b17aa20d3..921c0af47 100644
--- a/pipelined/src/cache/sram1rw.sv
+++ b/pipelined/src/cache/sram1rw.sv
@@ -46,6 +46,7 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
   logic 			 WriteEnableD;
 
     //*** model as single port
+    // *** merge with simpleram
     always_ff @(posedge clk) begin
       AddrD <= Adr;
       WriteDataD <= WriteData;    /// ****** this is not right. there should not need to be a delay.  Implement alternative cache stall to avoid this.  Eliminates a bunch of delay flops elsewhere
diff --git a/pipelined/src/generic/flop/simpleram.sv b/pipelined/src/generic/flop/simpleram.sv
index 43b873567..3ad367bd5 100644
--- a/pipelined/src/generic/flop/simpleram.sv
+++ b/pipelined/src/generic/flop/simpleram.sv
@@ -40,18 +40,14 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
 
   logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
   
-  /* verilator lint_off WIDTH */
-  if (`XLEN == 64)  begin:ramrw
-    always_ff @(posedge clk) begin
-      rd <= RAM[a[31:3]];
-      if (we) RAM[a[31:3]] <= #1 wd;
-    end
-  end else begin 
-    always_ff @(posedge clk) begin:ramrw
-      rd <= RAM[a[31:2]];
-      if (we) RAM[a[31:2]] <= #1 wd;
-    end
+  // discard bottom 2 or 3 bits of address offset within word or doubleword
+  localparam adrlsb = (`XLEN==64) ? 3 : 2;
+  logic [31:adrlsb] adrmsbs;
+  assign adrmsbs = a[31:adrlsb];
+
+  always_ff @(posedge clk) begin
+    rd <= RAM[adrmsbs];
+    if (we) RAM[adrmsbs] <= #1 wd;
   end
-  /* verilator lint_on WIDTH */
 endmodule