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initial work on dm for FP regs in debug spec

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James Stine 2024-06-06 18:12:43 -05:00
parent cd7624fb97
commit 12a4f2b97e
1 changed files with 56 additions and 52 deletions
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108
src/debug/dm.sv
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@ -26,31 +26,37 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module dm import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic rst,
input logic clk,
input logic rst,
// External JTAG signals
input logic tck,
input logic tdi,
input logic tms,
output logic tdo,
input logic tck,
input logic tdi,
input logic tms,
output logic tdo,
// Platform reset signal
output logic NdmReset,
output logic NdmReset,
// Core hazard signal
output logic DebugStall,
output logic DebugStall,
// Scan Chain
output logic ScanEn,
input logic ScanIn,
output logic ScanOut,
output logic GPRSel,
output logic DebugCapture,
output logic DebugGPRUpdate,
output logic [4:0] GPRAddr,
output logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
output logic ScanEn,
input logic ScanIn,
output logic ScanOut,
output logic GPRSel,
output logic DebugCapture,
output logic DebugGPRUpdate,
output logic [4:0] GPRAddr,
output logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut,
output logic FPRSel,
output logic DebugFPRUpdate,
output logic [4:0] FPRAddr,
output logic FPRScanEn,
input logic FPRScanIn,
output logic FPRScanOut
);
`include "debug.vh"
@ -114,46 +120,45 @@ module dm import cvw::*; #(parameter cvw_t P) (
logic [31:0] Data2Wr; // Muxed inputs to DataX regs
logic [31:0] Data3Wr; // Muxed inputs to DataX regs
// message registers
logic [31:0] Data0; // 0x04
logic [31:0] Data1; // 0x05
logic [31:0] Data2; // 0x06
logic [31:0] Data3; // 0x07
logic [31:0] Data0; // 0x04
logic [31:0] Data1; // 0x05
logic [31:0] Data2; // 0x06
logic [31:0] Data3; // 0x07
// debug module registers
logic [31:0] DMControl; // 0x10
logic [31:0] DMStatus; // 0x11
logic [31:0] AbstractCS; // 0x16
logic [31:0] SysBusCS; // 0x38
logic [31:0] DMControl; // 0x10
logic [31:0] DMStatus; // 0x11
logic [31:0] AbstractCS; // 0x16
logic [31:0] SysBusCS; // 0x38
//// DM register fields
// DMControl
logic AckUnavail;
logic DmActive; // This bit is used to (de)activate the DM. Toggling acts as reset
logic AckUnavail;
logic DmActive; // This bit is used to (de)activate the DM. Toggling acts as reset
// DMStatus
logic StickyUnavail;
logic ImpEBreak;
logic AllResumeAck;
logic AnyResumeAck;
logic AllNonExistent;
logic AnyNonExistent;
logic AllUnavail; // TODO
logic AnyUnavail;
logic AllRunning;
logic AnyRunning;
logic AllHalted;
logic AnyHalted;
const logic Authenticated = 1;
logic AuthBusy;
const logic HasResetHaltReq = 1;
logic ConfStrPtrValid;
const logic [3:0] Version = 3; // DM Version
logic StickyUnavail;
logic ImpEBreak;
logic AllResumeAck;
logic AnyResumeAck;
logic AllNonExistent;
logic AnyNonExistent;
logic AllUnavail; // TODO
logic AnyUnavail;
logic AllRunning;
logic AnyRunning;
logic AllHalted;
logic AnyHalted;
const logic Authenticated = 1;
logic AuthBusy;
const logic HasResetHaltReq = 1;
logic ConfStrPtrValid;
const logic [3:0] Version = 3; // DM Version
// AbstractCS
const logic [4:0] ProgBufSize = 0;
logic Busy;
const logic RelaxedPriv = 1;
logic [2:0] CmdErr;
const logic [3:0] DataCount = (P.XLEN/32);
const logic [4:0] ProgBufSize = 0;
logic Busy;
const logic RelaxedPriv = 1;
logic [2:0] CmdErr;
const logic [3:0] DataCount = (P.XLEN/32);
// Pack registers
assign DMControl = {2'b0, 1'b0, 2'b0, 1'b0, 10'b0,
@ -357,7 +362,6 @@ module dm import cvw::*; #(parameter cvw_t P) (
end
end
// Abstract command engine
// Due to length of the register scan chain,
// abstract commands execute independently of other DM operations