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mod wallypipelinedcore/soc for FP debug of regs

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This commit is contained in:
James Stine 2024-06-06 17:58:53 -05:00
parent 1d5ce9d21e
commit cd7624fb97
2 changed files with 30 additions and 6 deletions
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20
src/wally/wallypipelinedcore.sv
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@ -56,7 +56,13 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
input logic [4:0] GPRAddr,
input logic GPRScanEn,
input logic GPRScanIn,
output logic GPRScanOut
output logic GPRScanOut,
input logic FPRSel,
input logic DebugFPRUpdate,
input logic [4:0] FPRAddr,
input logic FPRScanEn,
input logic FPRScanIn,
output logic FPRScanOut
);
logic StallF, StallD, StallE, StallM, StallW;
@ -372,7 +378,17 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
.IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
.SetFflagsM, // FPU flags (to privileged unit)
.FIntDivResultW);
.FIntDivResultW,
.DebugScanEn,
.DebugScanIn(ScanReg[2]),
.DebugScanOut(ScanReg[3]),
.FPRSel,
.DebugCapture,
.DebugFPRUpdate,
.FPRAddr,
.FPRScanEn,
.FPRScanIn,
.FPRScanOut);
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW,
IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,

16
src/wally/wallypipelinedsoc.sv
View File

@ -86,6 +86,12 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
logic GPRScanEn;
logic GPRScanIn;
logic GPRScanOut;
logic FPRSel;
logic DebugFPRUpdate;
logic [4:0] FPRAddr;
logic FPRScanEn;
logic FPRScanIn;
logic FPRScanOut;
// synchronize reset to SOC clock domain
synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
@ -96,8 +102,8 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
.DebugStall, .DebugScanEn(ScanEn), .DebugScanIn(ScanOut), .DebugScanOut(ScanIn),
.GPRSel, .DebugCapture, .DebugGPRUpdate, .GPRAddr, .GPRScanEn, .GPRScanIn(GPRScanOut), .GPRScanOut(GPRScanIn)
);
.GPRSel, .DebugCapture, .DebugGPRUpdate, .GPRAddr, .GPRScanEn, .GPRScanIn(GPRScanOut), .GPRScanOut(GPRScanIn),
.FPRSel, .DebugFPRUpdate, .FPRAddr, .FPRScanEn, .FPRScanIn, .FPRScanOut);
// instantiate uncore if a bus interface exists
if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
@ -115,9 +121,11 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
if (P.DEBUG_SUPPORTED) begin : dm
dm #(P) dm (.clk, .rst(reset), .NdmReset, .tck, .tdi, .tms, .tdo,
.DebugStall, .ScanEn, .ScanIn, .ScanOut, .GPRSel, .DebugCapture, .DebugGPRUpdate,
.GPRAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut);
.GPRAddr, .GPRScanEn, .GPRScanIn, .GPRScanOut, .FPRSel, .DebugFPRUpdate,
.FPRAddr, .FPRScanEn, .FPRScanIn, .FPRScanOut);
end else begin
assign {NdmReset, DebugStall, ScanOut, GPRSel, DebugCapture, DebugGPRUpdate, GPRAddr, GPRScanEn, GPRScanOut} = '0;
assign {NdmReset, DebugStall, ScanOut, GPRSel, DebugCapture, DebugGPRUpdate, GPRAddr, GPRScanEn, GPRScanOut,
FPRSel, DebugFPRUpdate, FPRAddr, FPRScanEn, FPRScanOut} = '0;
end
endmodule