More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.

src/ebu/ahbinterface.sv

@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module ahbinterface #(
   parameter XLEN,
   parameter LSU = 0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
@@ -38,30 +36,30 @@ module ahbinterface #(
   input  logic                          HREADY,       // AHB peripheral ready
   output logic [1:0]                    HTRANS,       // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
   output logic                          HWRITE,       // AHB 0: Read operation 1: Write operation 
-  input  logic [`XLEN-1:0]              HRDATA,       // AHB read data
+  input  logic [XLEN-1:0]              HRDATA,       // AHB read data
-  output logic [`XLEN-1:0]              HWDATA,       // AHB write data
+  output logic [XLEN-1:0]              HWDATA,       // AHB write data
-  output logic [`XLEN/8-1:0]            HWSTRB,       // AHB byte mask
+  output logic [XLEN/8-1:0]            HWSTRB,       // AHB byte mask
   
   // lsu/ifu interface
   input  logic                          Stall,        // Core pipeline is stalled
   input  logic                          Flush,        // Pipeline stage flush. Prevents bus transaction from starting
   input  logic [1:0]                    BusRW,        // Memory operation read/write control: 10: read, 01: write
-  input  logic [`XLEN/8-1:0]            ByteMask,     // Bytes enables within a word
+  input  logic [XLEN/8-1:0]            ByteMask,     // Bytes enables within a word
-  input  logic [`XLEN-1:0]              WriteData,    // IEU write data for a store
+  input  logic [XLEN-1:0]              WriteData,    // IEU write data for a store
   output logic                          BusStall,     // Bus is busy with an in flight memory operation
   output logic                          BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
-  output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer   // Register to hold HRDATA after arriving from the bus
+  output logic [(LSU ? XLEN : 32)-1:0] FetchBuffer   // Register to hold HRDATA after arriving from the bus
 );
   
   logic                                 CaptureEn;
-  localparam                            LEN = (LSU ? `XLEN : 32);   // 32 bits for IFU, XLEN for LSU
+  localparam                            LEN = (LSU ? XLEN : 32);   // 32 bits for IFU, XLEN for LSU
   
   flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer));
 
   if(LSU) begin
     // delay HWDATA by 1 cycle per spec; assumes AHBW = XLEN    
-    flop #(`XLEN)   wdreg(HCLK, WriteData, HWDATA); 
+    flop #(XLEN)   wdreg(HCLK, WriteData, HWDATA); 
-    flop #(`XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
+    flop #(XLEN/8) HWSTRBReg(HCLK, ByteMask, HWSTRB);
   end else begin
     assign HWDATA = '0;
     assign HWSTRB = '0;

src/ebu/busfsm.sv

@@ -27,8 +27,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 // HCLK and clk must be the same clock!
 module busfsm (
   input  logic       HCLK,

src/ebu/controllerinput.sv

@@ -31,9 +31,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module controllerinput #(
+  parameter PA_BITS, 
   parameter SAVE_ENABLED = 1           // 1: Save manager inputs if Save = 1, 0: Don't save inputs
 )(
   input  logic                HCLK, 
@@ -47,14 +46,14 @@ module controllerinput #(
   input  logic                HWRITEIn,  // Manager input. AHB 0: Read operation 1: Write operation 
   input  logic [2:0]          HSIZEIn,   // Manager input. AHB transaction width
   input  logic [2:0]          HBURSTIn,  // Manager input. AHB burst length
-  input  logic [`PA_BITS-1:0] HADDRIn,   // Manager input. AHB address
+  input  logic [PA_BITS-1:0] HADDRIn,   // Manager input. AHB address
   output logic                HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
   // controller output
   output logic [1:0]          HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
   output logic                HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation 
   output logic [2:0]          HSIZEOut,  // Arbitrated manager transaction. AHB transaction width
   output logic [2:0]          HBURSTOut, // Arbitrated manager transaction. AHB burst length 
-  output logic [`PA_BITS-1:0] HADDROut,  // Arbitrated manager transaction. AHB address
+  output logic [PA_BITS-1:0] HADDROut,  // Arbitrated manager transaction. AHB address
   input  logic                HREADYIn   // Peripheral ready
 );
 
@@ -62,13 +61,13 @@ module controllerinput #(
   logic [2:0]                 HSIZESave;
   logic [2:0]                 HBURSTSave;
   logic [1:0]                 HTRANSSave;
-  logic [`PA_BITS-1:0]        HADDRSave;
+  logic [PA_BITS-1:0]        HADDRSave;
 
   if (SAVE_ENABLED) begin
-    flopenr #(1+3+3+2+`PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
+    flopenr #(1+3+3+2+PA_BITS) SaveReg(HCLK, ~HRESETn, Save,
       {HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
       {HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave});
-    mux2 #(1+3+3+2+`PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
+    mux2 #(1+3+3+2+PA_BITS) RestorMux({HWRITEIn, HSIZEIn, HBURSTIn, HTRANSIn, HADDRIn}, 
       {HWRITESave, HSIZESave, HBURSTSave, HTRANSSave, HADDRSave},
       Restore,
       {HWRITEOut, HSIZEOut, HBURSTOut, HTRANSOut, HADDROut});

src/ebu/ebu.sv

@@ -31,33 +31,31 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
+module ebu #(parameter XLEN, PA_BITS, AHBW)(
-
-module ebu (
   input  logic                clk, reset,
   // Signals from IFU
   input  logic [1:0]          IFUHTRANS, // IFU AHB transaction request
   input  logic [2:0]          IFUHSIZE,  // IFU AHB transaction size
   input  logic [2:0]          IFUHBURST, // IFU AHB burst length
-  input  logic [`PA_BITS-1:0] IFUHADDR,  // IFU AHB address
+  input  logic [PA_BITS-1:0] IFUHADDR,  // IFU AHB address
   output logic                IFUHREADY, // AHB peripheral ready gated by possible non-grant
   // Signals from LSU
   input  logic [1:0]          LSUHTRANS, // LSU AHB transaction request
   input  logic                LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read
   input  logic [2:0]          LSUHSIZE,  // LSU AHB size
   input  logic [2:0]          LSUHBURST, // LSU AHB burst length
-  input  logic [`PA_BITS-1:0] LSUHADDR,  // LSU AHB address
+  input  logic [PA_BITS-1:0] LSUHADDR,  // LSU AHB address
-  input  logic [`XLEN-1:0]    LSUHWDATA, // initially support AHBW = XLEN
+  input  logic [XLEN-1:0]    LSUHWDATA, // initially support AHBW = XLEN
-  input  logic [`XLEN/8-1:0]  LSUHWSTRB, // AHB byte mask
+  input  logic [XLEN/8-1:0]  LSUHWSTRB, // AHB byte mask
   output logic                LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
 
   // AHB-Lite external signals
   output logic                HCLK, HRESETn, 
   input  logic                HREADY,    // AHB peripheral ready
   input  logic                HRESP,     // AHB peripheral response. 0: OK 1: Error
-  output logic [`PA_BITS-1:0] HADDR,     // AHB address to peripheral after arbitration
+  output logic [PA_BITS-1:0] HADDR,     // AHB address to peripheral after arbitration
-  output logic [`AHBW-1:0]    HWDATA,    // AHB Write data after arbitration
+  output logic [AHBW-1:0]    HWDATA,    // AHB Write data after arbitration
-  output logic [`XLEN/8-1:0]  HWSTRB,    // AHB byte write enables after arbitration
+  output logic [XLEN/8-1:0]  HWSTRB,    // AHB byte write enables after arbitration
   output logic                HWRITE,    // AHB transaction direction after arbitration
   output logic [2:0]          HSIZE,     // AHB transaction size after arbitration
   output logic [2:0]          HBURST,    // AHB burst length after arbitration
@@ -73,13 +71,13 @@ module ebu (
   logic                       IFUDisable;
   logic                       IFUSelect;
 
-  logic [`PA_BITS-1:0]        IFUHADDROut;
+  logic [PA_BITS-1:0]        IFUHADDROut;
   logic [1:0]                 IFUHTRANSOut;
   logic [2:0]                 IFUHBURSTOut;
   logic [2:0]                 IFUHSIZEOut;
   logic                       IFUHWRITEOut;
   
-  logic [`PA_BITS-1:0]        LSUHADDROut;
+  logic [PA_BITS-1:0]        LSUHADDROut;
   logic [1:0]                 LSUHTRANSOut;
   logic [2:0]                 LSUHBURSTOut;
   logic [2:0]                 LSUHSIZEOut;
@@ -98,14 +96,14 @@ module ebu (
   // input stages and muxing for IFU and LSU
   ////////////////////////////////////////////////////////////////////////////////////////////////////
 
-  controllerinput IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
+  controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable),
     .Request(IFUReq),
     .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR),
     .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
     .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY));
 
   // LSU always has priority so there should never be a need to save and restore the address phase inputs.
-  controllerinput #(0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
+  controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable),
     .Request(LSUReq),
     .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY),
     .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),

src/ebu/ebufsmarb.sv

@@ -28,8 +28,6 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
-`include "wally-config.vh"
-
 module ebufsmarb (
   input  logic       HCLK,
   input  logic       HRESETn,

src/wally/wallypipelinedcore.sv

@@ -242,7 +242,7 @@ module wallypipelinedcore import cvw::*;  #(parameter cvw_t P) (
     .LSUStallM);                    
 
   if(P.BUS_SUPPORTED) begin : ebu
-    ebu ebu(// IFU connections
+    ebu #(P.XLEN, P.PA_BITS, P.AHBW) ebu(// IFU connections
       .clk, .reset,
       // IFU interface
       .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE,