diff --git a/addins/riscv-dv b/addins/riscv-dv
index a7e27bc04..f0c570d11 160000
--- a/addins/riscv-dv
+++ b/addins/riscv-dv
@@ -1 +1 @@
-Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172
+Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580
diff --git a/sim/questa/wally-imperas-cov.do b/sim/questa/wally-imperas-cov.do
index 4ddd3c229..d407cde0f 100644
--- a/sim/questa/wally-imperas-cov.do
+++ b/sim/questa/wally-imperas-cov.do
@@ -50,7 +50,7 @@ vlog +incdir+$env(WALLY)/config/$1 \
      +incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
      $env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv  \
     \
-    $env(WALLY)/src/cvw.sv \
+     $env(WALLY)/src/cvw.sv \
      $env(WALLY)/testbench/testbench-imperas.sv \
      $env(WALLY)/testbench/common/*.sv   \
      $env(WALLY)/src/*/*.sv \
diff --git a/site-setup.sh b/site-setup.sh
index a49889a9a..4af031e35 100755
--- a/site-setup.sh
+++ b/site-setup.sh
@@ -11,7 +11,7 @@
 # Must edit these based on your local environment.
 export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu                   # Change this to your Siemens license server for Questa
 export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu                # Change this to your Synopsys license server for Design Compiler
-export QUESTA_HOME=/cad/mentor/questa_sim-2023.4                    # Change this for your path to Questa, excluding bin
+export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim          # Change this for your path to Questa, excluding bin
 export DC_HOME=/cad/synopsys/SYN                                    # Change this for your path to Synopsys Design Compiler, excluding bin
 export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4                   # Change this for your path to Synopsys VCS, exccluding bin
 
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index b3dc17024..d3cff2e96 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -102,7 +102,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
 
   // outputs for the performance counters.
   assign CacheAccess = (|CacheRW) & ((CurrState == STATE_ACCESS & ~Stall & ~FlushStage) | (CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
-  assign CacheMiss = CacheAccess & ~Hit;
+  assign CacheMiss = CurrState == STATE_ADDRESS_SETUP & ~Stall & ~FlushStage;
 
   // special case on reset. When the fsm first exists reset twayhe
   // PCNextF will no longer be pointing to the correct address.