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Added csrwrites.S test case for privileged tests
This commit is contained in:
David Harris
parent
60d807f1b0
commit
121d1cea62
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vendored
@ -111,6 +111,5 @@ sim/imperas.log
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sim/results-error/
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sim/results-error/
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sim/test1.rep
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sim/test1.rep
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sim/vsim.log
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sim/vsim.log
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tests/coverage/*.S
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tests/coverage/*.elf
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tests/coverage/*.elf
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*.elf.memfile
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*.elf.memfile
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@ -130,10 +130,14 @@ tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64z
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"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
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"arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"]
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if (coverage): # delete all but 64gc tests when running coverage
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if (coverage): # delete all but 64gc tests when running coverage
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configs = []
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configs = []
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tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m",
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tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
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"arch64zi", "wally64a", "wally64periph", "wally64priv",
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"arch64zi", "wally64a", "wally64periph", "wally64priv",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
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"imperas64f", "imperas64d", "imperas64c", "imperas64i"]
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# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m",
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# "arch64zi", "wally64a", "wally64periph", "wally64priv",
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# "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
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# "imperas64f", "imperas64d", "imperas64c", "imperas64i"]
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coverStr = '-coverage'
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coverStr = '-coverage'
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else:
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else:
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coverStr = ''
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coverStr = ''
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@ -76,106 +76,84 @@ module bmuctrl(
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// Main Instruction Decoder
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// Main Instruction Decoder
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always_comb begin
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always_comb begin
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BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction
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casez({OpD, Funct7D, Funct3D})
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// ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
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// ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
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// ZBS
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BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction
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17'b0010011_0100100_001: if (`ZBS_SUPPORTED)
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if (`ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri
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casez({OpD, Funct7D, Funct3D})
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17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED)
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17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add
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BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64)
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17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add
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17'b0010011_0100100_101: if (`ZBS_SUPPORTED)
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17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add
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BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti
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endcase
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17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED)
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if (`ZBA_SUPPORTED & `XLEN==64)
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BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64)
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casez({OpD, Funct7D, Funct3D})
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17'b0010011_0110100_001: if (`ZBS_SUPPORTED)
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17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw
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BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi
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17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw
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17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED)
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17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw
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BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64)
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17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw
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17'b0010011_0010100_001: if (`ZBS_SUPPORTED)
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17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw
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BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti
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endcase
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17'b0010011_0010101_001: if (`XLEN == 64 & `ZBS_SUPPORTED)
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if (`ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64)
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0100100_001: if (`ZBS_SUPPORTED)
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17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol
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BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr
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17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror
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17'b0110011_0100100_101: if (`ZBS_SUPPORTED)
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17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010))
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BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext
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BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
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17'b0110011_0110100_001: if (`ZBS_SUPPORTED)
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else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
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BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv
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BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
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17'b0110011_0010100_001: if (`ZBS_SUPPORTED)
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17'b0110011_0000100_100: if (`XLEN == 32)
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BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset
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BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
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17'b0110011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
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BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
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17'b0010011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor
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BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli
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17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
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17'b0111011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8
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BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw
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17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
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17'b0011011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b
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BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu
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endcase
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if (`ZBB_SUPPORTED & `XLEN==64)
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casez({OpD, Funct7D, Funct3D})
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17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw
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17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw
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17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64)
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17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw
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17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
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BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction
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17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64)
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endcase
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if (`ZBC_SUPPORTED)
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction
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endcase
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if (`ZBS_SUPPORTED) // ZBS
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casez({OpD, Funct7D, Funct3D})
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17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri
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17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti
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17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi
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17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti
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17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr
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17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext
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17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv
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17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset
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endcase
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if (`ZBS_SUPPORTED & `XLEN==64) // ZBS 64-bit
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casez({OpD, Funct7D, Funct3D})
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17'b0010011_0100101_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64)
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17'b0010011_0100101_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64)
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17'b0010011_0110101_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64)
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17'b0010011_0010101_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64)
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endcase
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if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need certain BMU shifter control when BMU shifter is used
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll
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17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli
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17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw
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17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw
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endcase
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// ZBC
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// ZBC
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17'b0110011_0000101_0??: if (`ZBC_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction
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// ZBA
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17'b0110011_0010000_010: if (`ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add
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17'b0110011_0010000_100: if (`ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add
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17'b0110011_0010000_110: if (`ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add
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17'b0111011_0010000_010: if (`XLEN == 64 & `ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw
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17'b0111011_0010000_100: if (`XLEN == 64 & `ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw
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17'b0111011_0010000_110: if (`XLEN == 64 & `ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw
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17'b0111011_0000100_000: if (`XLEN == 64 & `ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw
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17'b0011011_000010?_001: if (`XLEN == 64 & `ZBA_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw
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// ZBB
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17'b0110011_0110000_001: if (`ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol
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17'b0111011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw
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17'b0110011_0110000_101: if (`ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror
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17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw
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//17'b0010011_0110000_101: if (`ZBB_SUPPORTED)
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// BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32)
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17'b0010011_011000?_101: if ((`XLEN == 64 | ~Funct7D[0]) & `ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64)
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17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw
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17'b0010011_0110000_001: if (`ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010))
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BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
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else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])))
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BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
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17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])))
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BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction
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17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED)
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BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64)
|
|
||||||
17'b0110011_0000100_100: if (`XLEN == 32 & `ZBB_SUPPORTED)
|
|
||||||
BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
|
|
||||||
17'b0110011_0100000_111: if (`ZBB_SUPPORTED)
|
|
||||||
BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
|
|
||||||
17'b0110011_0100000_110: if (`ZBB_SUPPORTED)
|
|
||||||
BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
|
|
||||||
17'b0110011_0100000_100: if (`ZBB_SUPPORTED)
|
|
||||||
BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor
|
|
||||||
17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000))
|
|
||||||
BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8
|
|
||||||
17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111)
|
|
||||||
BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b
|
|
||||||
17'b0110011_0000101_110: if (`ZBB_SUPPORTED)
|
|
||||||
BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max
|
|
||||||
17'b0110011_0000101_111: if (`ZBB_SUPPORTED)
|
|
||||||
BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu
|
|
||||||
17'b0110011_0000101_100: if (`ZBB_SUPPORTED)
|
|
||||||
BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min
|
|
||||||
17'b0110011_0000101_101: if (`ZBB_SUPPORTED)
|
|
||||||
BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu
|
|
||||||
endcase
|
|
||||||
end
|
end
|
||||||
|
|
||||||
// Unpack Control Signals
|
// Unpack Control Signals
|
||||||
|
|||||||
@ -100,10 +100,10 @@ module csrs #(parameter
|
|||||||
else
|
else
|
||||||
assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
|
assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
|
||||||
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
|
flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
|
||||||
if (`SSTC_SUPPORTED) begin
|
if (`SSTC_SUPPORTED) begin : sstc
|
||||||
if (`XLEN == 64)
|
if (`XLEN == 64) begin : sstc64
|
||||||
flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW);
|
flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW);
|
||||||
else begin
|
end else begin : sstc32
|
||||||
flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]);
|
flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]);
|
||||||
flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]);
|
flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]);
|
||||||
end
|
end
|
||||||
|
|||||||
@ -44,7 +44,8 @@ string tvpaths[] = '{
|
|||||||
|
|
||||||
string coverage64gc[] = '{
|
string coverage64gc[] = '{
|
||||||
`COVERAGE,
|
`COVERAGE,
|
||||||
"badinstr"
|
"badinstr",
|
||||||
|
"csrwrites"
|
||||||
};
|
};
|
||||||
|
|
||||||
string coremark[] = '{
|
string coremark[] = '{
|
||||||
|
|||||||
@ -15,12 +15,11 @@ all: $(OBJECTS)
|
|||||||
|
|
||||||
%.elf.objdump: %.elf
|
%.elf.objdump: %.elf
|
||||||
|
|
||||||
|
# Change many things if bit width isn't 64
|
||||||
%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
|
%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
|
||||||
# Change many things if bit width isn't 64
|
|
||||||
echo $@
|
|
||||||
riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \
|
riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \
|
||||||
-nostartfiles -T../../examples/link/link.ld $<
|
-nostartfiles -T../../examples/link/link.ld $<
|
||||||
riscv64-unknown-elf-objdump -D $@ > $@.objdump
|
riscv64-unknown-elf-objdump -S $@ > $@.objdump
|
||||||
riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
|
riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
|
||||||
extractFunctionRadix.sh $@.objdump
|
extractFunctionRadix.sh $@.objdump
|
||||||
|
|
||||||
|
|||||||
35
tests/coverage/csrwrites.S
Normal file
35
tests/coverage/csrwrites.S
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
///////////////////////////////////////////
|
||||||
|
// csrwrites.S
|
||||||
|
//
|
||||||
|
// Written: David_Harris@hmc.edu 21 March 2023
|
||||||
|
//
|
||||||
|
// Purpose: Test writes to CSRs
|
||||||
|
//
|
||||||
|
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||||
|
//
|
||||||
|
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||||
|
//
|
||||||
|
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||||
|
//
|
||||||
|
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||||
|
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||||
|
// may obtain a copy of the License at
|
||||||
|
//
|
||||||
|
// https://solderpad.org/licenses/SHL-2.1/
|
||||||
|
//
|
||||||
|
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||||
|
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||||
|
// either express or implied. See the License for the specific language governing permissions
|
||||||
|
// and limitations under the License.
|
||||||
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
// load code to initalize stack, handle interrupts, terminate
|
||||||
|
#include "WALLY-init-lib.h"
|
||||||
|
|
||||||
|
main:
|
||||||
|
csrrw t0, stimecmp, t0
|
||||||
|
csrrw t0, satp, t0
|
||||||
|
csrrw t0, stvec, t0
|
||||||
|
csrrw t0, sscratch, t0
|
||||||
|
|
||||||
|
j done
|
||||||
Loading…
Reference in New Issue
Block a user