From 121d1cea62edb765a3a83483e0729b48a7b892ba Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 10:55:32 -0700 Subject: [PATCH] Added csrwrites.S test case for privileged tests --- .gitignore | 1 - sim/regression-wally | 6 +- src/ieu/bmu/bmuctrl.sv | 174 ++++++++++++++++--------------------- src/privileged/csrs.sv | 6 +- testbench/tests.vh | 3 +- tests/coverage/Makefile | 5 +- tests/coverage/csrwrites.S | 35 ++++++++ 7 files changed, 123 insertions(+), 107 deletions(-) create mode 100644 tests/coverage/csrwrites.S diff --git a/.gitignore b/.gitignore index 1f8e8b158..6e9920603 100644 --- a/.gitignore +++ b/.gitignore @@ -111,6 +111,5 @@ sim/imperas.log sim/results-error/ sim/test1.rep sim/vsim.log -tests/coverage/*.S tests/coverage/*.elf *.elf.memfile \ No newline at end of file diff --git a/sim/regression-wally b/sim/regression-wally index 77ab05c15..122b04b51 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -130,10 +130,14 @@ tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64z "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] - tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", + tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] +# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", +# "arch64zi", "wally64a", "wally64periph", "wally64priv", +# "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", +# "imperas64f", "imperas64d", "imperas64c", "imperas64i"] coverStr = '-coverage' else: coverStr = '' diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ae401ef88..645e711cc 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -76,106 +76,84 @@ module bmuctrl( // Main Instruction Decoder always_comb begin - BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction - casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD - // ZBS - 17'b0010011_0100100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_0100100_101: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti - 17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_0110100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi - 17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - 17'b0010011_0010100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti - 17'b0010011_0010101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) - 17'b0110011_0100100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset - 17'b0110011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction + if (`ZBA_SUPPORTED) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add + endcase + if (`ZBA_SUPPORTED & `XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw + endcase + if (`ZBB_SUPPORTED) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror + 17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010)) + BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction + else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction + 17'b0110011_0000100_100: if (`XLEN == 32) + BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor + 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000)) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 + 17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu + endcase + if (`ZBB_SUPPORTED & `XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) + 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw + 17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) + endcase + if (`ZBC_SUPPORTED) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction + endcase + if (`ZBS_SUPPORTED) // ZBS + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset + endcase + if (`ZBS_SUPPORTED & `XLEN==64) // ZBS 64-bit + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0100101_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) + 17'b0010011_0100101_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) + 17'b0010011_0110101_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) + 17'b0010011_0010101_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) + endcase + if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need certain BMU shifter control when BMU shifter is used + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + endcase // ZBC - 17'b0110011_0000101_0??: if (`ZBC_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction - // ZBA - 17'b0110011_0010000_010: if (`ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: if (`ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: if (`ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add - 17'b0111011_0010000_010: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw - // ZBB - 17'b0110011_0110000_001: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - //17'b0010011_0110000_101: if (`ZBB_SUPPORTED) - // BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) - 17'b0010011_011000?_101: if ((`XLEN == 64 | ~Funct7D[0]) & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - 17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0010011_0110000_001: if (`ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010)) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction - else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction - 17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - 17'b0110011_0000100_100: if (`XLEN == 32 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) - 17'b0110011_0100000_111: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 - 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu - endcase end // Unpack Control Signals diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 1a5906653..b13b620b0 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -100,10 +100,10 @@ module csrs #(parameter else assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); - if (`SSTC_SUPPORTED) begin - if (`XLEN == 64) + if (`SSTC_SUPPORTED) begin : sstc + if (`XLEN == 64) begin : sstc64 flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW); - else begin + end else begin : sstc32 flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]); flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]); end diff --git a/testbench/tests.vh b/testbench/tests.vh index 67152fe7c..83729f964 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -44,7 +44,8 @@ string tvpaths[] = '{ string coverage64gc[] = '{ `COVERAGE, - "badinstr" + "badinstr", + "csrwrites" }; string coremark[] = '{ diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 8742dee63..d3686f8eb 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -15,12 +15,11 @@ all: $(OBJECTS) %.elf.objdump: %.elf +# Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - # Change many things if bit width isn't 64 - echo $@ riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< - riscv64-unknown-elf-objdump -D $@ > $@.objdump + riscv64-unknown-elf-objdump -S $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile extractFunctionRadix.sh $@.objdump diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S new file mode 100644 index 000000000..76e310e5f --- /dev/null +++ b/tests/coverage/csrwrites.S @@ -0,0 +1,35 @@ +/////////////////////////////////////////// +// csrwrites.S +// +// Written: David_Harris@hmc.edu 21 March 2023 +// +// Purpose: Test writes to CSRs +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + csrrw t0, stimecmp, t0 + csrrw t0, satp, t0 + csrrw t0, stvec, t0 + csrrw t0, sscratch, t0 + + j done