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https://github.com/openhwgroup/cvw
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Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
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@ -185,12 +185,12 @@ module ifu (
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assign InstrRawF = AllInstrRawF[31:0];
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assign InstrRawF = AllInstrRawF[31:0];
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if (`IROM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM
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if (`IROM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM
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dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM({{(`XLEN-32){1'b0}}, PCPF[31:0]}), .IEUAdrE(PCNextFSpill),
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irom irom(.clk, .reset, .LSURWM(2'b10), .IEUAdrE(PCNextFSpill),
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.TrapM(1'b0), .WriteDataM(), .ByteMaskM('0),
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.TrapM(1'b0),
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.ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
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.ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}));
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.BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF),
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.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
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assign {BusStall, IFUBusRead} = '0;
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assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
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end
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end
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if (`IBUS) begin : bus
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if (`IBUS) begin : bus
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localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
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localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
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@ -31,23 +31,13 @@
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module dtim(
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module dtim(
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input logic clk, reset,
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input logic clk, reset,
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input logic CPUBusy,
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input logic [1:0] LSURWM,
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input logic [1:0] LSURWM,
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input logic [`XLEN-1:0] IEUAdrM,
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input logic [`XLEN-1:0] IEUAdrE,
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input logic [`XLEN-1:0] IEUAdrE,
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input logic TrapM,
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input logic TrapM,
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input logic [`LLEN-1:0] WriteDataM,
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input logic [`LLEN-1:0] WriteDataM,
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input logic [`LLEN/8-1:0] ByteMaskM,
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input logic [`LLEN/8-1:0] ByteMaskM,
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input logic Cacheable,
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input logic Cacheable,
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output logic [`LLEN-1:0] ReadDataWordM,
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output logic [`LLEN-1:0] ReadDataWordM
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output logic BusStall,
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output logic LSUBusWrite,
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output logic LSUBusRead,
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output logic BusCommittedM,
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output logic DCacheStallM,
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output logic DCacheCommittedM,
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output logic DCacheMiss,
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output logic DCacheAccess
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);
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);
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logic we;
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logic we;
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@ -60,12 +50,5 @@ module dtim(
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bram1p1rw #(`LLEN/8, 8, ADDR_WDITH)
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bram1p1rw #(`LLEN/8, 8, ADDR_WDITH)
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ram(.clk, .we, .bwe(ByteMaskM), .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
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ram(.clk, .we, .bwe(ByteMaskM), .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
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// since we have a local memory the bus connections are all disabled.
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// There are no peripherals supported.
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assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
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assign {DCacheStallM, DCacheCommittedM} = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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endmodule
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endmodule
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@ -200,10 +200,15 @@ module lsu (
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// use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore.
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// use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore.
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if (`DMEM) begin : dtim
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if (`DMEM) begin : dtim
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dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData
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dtim dtim(.clk, .reset, .LSURWM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData - is this done already?
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.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
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.ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM));
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.DCacheStallM, .DCacheCommittedM, .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM),
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.DCacheMiss, .DCacheAccess);
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// since we have a local memory the bus connections are all disabled.
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// There are no peripherals supported.
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// *** this will have to change to support TIM and bus (DH 8/25/22)
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assign {BusStall, LSUBusWrite, LSUBusRead, BusCommittedM} = '0;
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assign {DCacheStallM, DCacheCommittedM} = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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end
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end
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if (`DBUS) begin : bus
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if (`DBUS) begin : bus
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localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
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localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
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