From 110b762b554adfe5a2964404a776d73383d04b49 Mon Sep 17 00:00:00 2001 From: cturek Date: Wed, 13 Jul 2022 17:56:23 +0000 Subject: [PATCH] Finalized sqrt, ready for debugging --- pipelined/srt/srt.sv | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index f04aa718f..238692256 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -57,7 +57,7 @@ module srt ( logic qp, qz, qm; // quotient is +1, 0, or -1 logic [`NE-1:0] calcExp; logic calcSign; - logic [`DIVLEN+3:0] X, Dpreproc, C; + logic [`DIVLEN+3:0] X, Dpreproc, C, F, AddIn; logic [`DIVLEN+3:0] WS, WSA, WSN, WC, WCA, WCN, D, Db, Dsel; logic [$clog2(`XLEN+1)-1:0] intExp, dur, calcDur; logic intSign; @@ -87,17 +87,19 @@ module srt ( // Divisor Selection logic assign Db = ~D; mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel); - fsel2 fsel(qp, qn, ) + + // If only implementing division, use divide otfc + // otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot); + // otherwise use sotfc + creg sotfcC(clk, Start, C); + sotfc2 #(`DIVLEN) sotfc2(clk, Start, qp, qn, C, Quot, F); + + // Adder input selection + assign AddIn = Sqrt ? F : Dsel; // Partial Product Generation - csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA); + csa #(`DIVLEN+4) csa(WS, WC, AddIn, qp, WSA, WCA); - // If only implementing division, use divide otfc - otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot); - // otherwise use sotfc - // creg sotfcC(clk, Start, C); - // sotfc2 #(`DIVLEN) sotfc2(clk, Start, qp, qn, C, Quot, F); - expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt); signcalc signcalc(.XSign, .YSign, .calcSign);