diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do
index a933a8445..63c2e64f9 100644
--- a/wally-pipelined/regression/wally-coremark_bare.do
+++ b/wally-pipelined/regression/wally-coremark_bare.do
@@ -111,6 +111,6 @@ set DefaultRadix hexadecimal
 -- Run the Simulation 
 #run 7402000
 #run 12750
-#run -all
-run 5000
+run -all
+#run 21400
 #quit
diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index 1bc6f64d0..ca9ed7aad 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -48,7 +48,7 @@ module testbench();
   
   // pick tests based on modes supported
   initial 
-  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"};
+  tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"};
   string signame, memfilename;
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
@@ -76,8 +76,8 @@ module testbench();
       $readmemh(memfilename, dut.uncore.dtim.RAM);
       for(j=268437829; j < 268566528; j = j+1)
         dut.uncore.dtim.RAM[j] = 64'b0;
-//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr";
-//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab";
+//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
+//      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
       reset = 1; # 22; reset = 0;
     end
   // generate clock to sequence tests