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cacheway cleanup

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This commit is contained in:
David Harris 2022-02-03 16:07:55 +00:00
parent c22f7eb11c
commit 0fbc32204c
2 changed files with 3 additions and 20 deletions
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18
pipelined/src/cache/cacheway.sv vendored
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@ -117,14 +117,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= #1 1'b1; else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= #1 1'b1;
else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= #1 1'b0; else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= #1 1'b0;
end end
/* always_ff @(posedge clk) begin // pipeline register; helps timing ***Ross consider further
RAdrD <= #1 RAdr;
SetValidD <= #1 SetValid;
ClearValidD <= #1 ClearValid;
WriteEnableD <= #1 WriteEnable;
VDWriteEnableD <= #1 VDWriteEnable;
end */
flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
flop #(4) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable, VDWriteEnable}, flop #(4) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable, VDWriteEnable},
{SetValidD, ClearValidD, WriteEnableD, VDWriteEnableD}); {SetValidD, ClearValidD, WriteEnableD, VDWriteEnableD});
@ -142,16 +134,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b0; else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b0;
end end
flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD}); flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
/* always_ff @(posedge clk) begin
SetDirtyD <= SetDirty;
ClearDirtyD <= ClearDirty;
end */
assign Dirty = DirtyBits[RAdrD]; assign Dirty = DirtyBits[RAdrD];
end else begin:dirty end else assign Dirty = 1'b0;
assign Dirty = 1'b0;
end
endmodule // DCacheCacheWays endmodule // DCacheCacheWays

5
pipelined/src/ieu/datapath.sv
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@ -125,7 +125,7 @@ module datapath (
// Writeback stage pipeline register and logic // Writeback stage pipeline register and logic
flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW); flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW);
flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW); flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
flopen #(`XLEN) ReadDataWReg(.clk, .en(~StallW), .d(ReadDataM), .q(ReadDataW)); flopen #(`XLEN) ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW);
mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, WriteDataW); mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, WriteDataW);
// floating point interactions: fcvt, fp stores // floating point interactions: fcvt, fp stores
@ -133,8 +133,7 @@ module datapath (
mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM); mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
end else begin:fpmux end else begin:fpmux
assign ResultM = IEUResultM; assign ResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE;
assign WriteDataE = ForwardedSrcBE;
end end
// handle Store Conditional result if atomic extension supported // handle Store Conditional result if atomic extension supported