From 0fbc32204ce1fca81586029a3c18a71a7ed001ee Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 3 Feb 2022 16:07:55 +0000
Subject: [PATCH] cacheway cleanup

---
 pipelined/src/cache/cacheway.sv | 18 +-----------------
 pipelined/src/ieu/datapath.sv   |  5 ++---
 2 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
index b0c9321fd..042a92fda 100644
--- a/pipelined/src/cache/cacheway.sv
+++ b/pipelined/src/cache/cacheway.sv
@@ -117,14 +117,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
     else if (SetValidD   & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= #1 1'b1;
     else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= #1 1'b0;
 	end
-
-/*  always_ff @(posedge clk) begin // pipeline register; helps timing ***Ross consider further
-    RAdrD          <= #1 RAdr;
-    SetValidD      <= #1 SetValid;
-    ClearValidD    <= #1 ClearValid;    
-    WriteEnableD   <= #1 WriteEnable;
-    VDWriteEnableD <= #1 VDWriteEnable;
-  end */
   flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
   flop #(4) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable, VDWriteEnable},
     {SetValidD, ClearValidD, WriteEnableD, VDWriteEnableD});
@@ -142,16 +134,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
       else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= #1 1'b0;
     end
     flop #(2) DirtyCtlDelayReg(clk, {SetDirty, ClearDirty}, {SetDirtyD, ClearDirtyD});
-/*    always_ff @(posedge clk) begin
-      SetDirtyD <= SetDirty;
-      ClearDirtyD <= ClearDirty;
-    end */
     assign Dirty = DirtyBits[RAdrD];
-  end else begin:dirty
-    assign Dirty = 1'b0;
-  end
-
-  
+  end else assign Dirty = 1'b0;
 endmodule // DCacheCacheWays
 
 
diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv
index 0c1ff3e32..aa43a5b19 100644
--- a/pipelined/src/ieu/datapath.sv
+++ b/pipelined/src/ieu/datapath.sv
@@ -125,7 +125,7 @@ module datapath (
   // Writeback stage pipeline register and logic
   flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW);
   flopenrc #(5)     RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
-  flopen #(`XLEN)   ReadDataWReg(.clk, .en(~StallW), .d(ReadDataM), .q(ReadDataW));
+  flopen #(`XLEN)   ReadDataWReg(clk, ~StallW, ReadDataM, ReadDataW);
   mux5  #(`XLEN)    resultmuxW(ResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, WriteDataW);	 
 
   // floating point interactions: fcvt, fp stores
@@ -133,8 +133,7 @@ module datapath (
     mux2  #(`XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
     mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
   end else begin:fpmux
-    assign ResultM = IEUResultM;
-    assign WriteDataE = ForwardedSrcBE;
+    assign ResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE;
   end
 
   // handle Store Conditional result if atomic extension supported