From 0e2efca490c2d71f38463e49e6985070f9a3d89c Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sat, 23 Oct 2021 10:02:47 -0500 Subject: [PATCH] Remove redundant logic value --- wally-pipelined/src/fpu/divconv_pipe.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/wally-pipelined/src/fpu/divconv_pipe.sv b/wally-pipelined/src/fpu/divconv_pipe.sv index 49496aa33..240000c28 100755 --- a/wally-pipelined/src/fpu/divconv_pipe.sv +++ b/wally-pipelined/src/fpu/divconv_pipe.sv @@ -66,8 +66,6 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r logic [59:0] d2, n2; logic [11:0] d3; - logic muxr_out, cout1, cout2, cout3, cout4, cout5, cout6, cout7; - // Check if exponent is odd for sqrt // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA assign d2 = (exp_odd&op_type) ? {vss, d, 6'h0} : {d, 7'h0};