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Code cleanup

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This commit is contained in:
David Harris 2022-01-07 04:07:04 +00:00
parent c9c3bddc6d
commit 0e023e29d8
10 changed files with 25 additions and 238 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86

2
bin/elf2hex.sh
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@ -1,4 +1,4 @@
#!/bin/sh #!/bin/bash
# james.stine@okstate.edu 4 Jan 2022 # james.stine@okstate.edu 4 Jan 2022
# Script to run elf2hex for memfile for # Script to run elf2hex for memfile for

170
bin/exe2memfile-deleteme.pl
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@ -1,170 +0,0 @@
#!/usr/bin/perl -w
# exe2memfile.pl
# David_Harris@hmc.edu 26 November 2020
# Converts an executable file to a series of 32-bit hex instructions
# to read into a Verilog simulation with $readmemh
use File::stat;
use IO::Handle;
if ($#ARGV == -1) {
die("Usage: $0 executable_file");
}
# array to hold contents of memory file
my $maxmemfilesize = 1000000;
my @memfilebytes = (0)*$maxmemfilesize*4;
my $maxaddress = 0;
STDOUT->autoflush(1);
my $numfiles = $#ARGV+1;
if ($numfiles > 1) {
print ("Processing $numfiles memfiles: ");
}
my $frac = $#ARGV/10;
for(my $i=0; $i<=$#ARGV; $i++) {
if ($i > 0 && ($i < 10 || $i % $frac == 0)) { print ("$i ") };
my $fname = $ARGV[$i];
# print "fname = $fname";
my $ofile = $fname.".objdump";
my $memfile = $fname.".memfile";
my $needsprocessing = 0;
if (!-e $memfile) { $needsprocessing = 1; } # create memfile if it doesn't exist
else {
my $osb = stat($ofile) || die("Can't stat $ofile");
my $msb = stat($memfile) || die("Can't stat $memfile");
my $otime = $osb->mtime;
my $mtime = $msb->mtime;
if ($otime > $mtime) { $needsprocessing = 1; } # is memfile out of date?
}
if ($needsprocessing == 1) {
open(FILE, $ofile) || die("Can't read $ofile");
my $mode = 0; # parse for code
my $address;
# initialize to all zeros;
for (my $i=0; $i < $maxmemfilesize*4; $i++) {
$memfilebytes[$i] = "00";
}
while(<FILE>) {
if ($mode == 0) { # Parse code
# print("Examining $_\n");
if (/^\s*(\S\S\S\S\S\S\S\S):\s+(\S+)\s+/) {
$address = &fixadr($1);
my $instr = $2;
my $len = length($instr);
for (my $i=0; $i<$len/2; $i++) {
$memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2);
}
# print ("address $address $instr\n");
}
if (/Disassembly of section .data:/) { $mode = 1;}
} elsif ($mode == 1) { # Parse data segment
# if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) { # changed to \t 30 Oct 2021 dmh to fix parsing issue in d_fmadd_b17
if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) {
$address = &fixadr($1);
# print "addresss $address maxaddress $maxaddress\n";
if ($address > $maxaddress) { $maxaddress = $address; }
#print "test $address $1 $2\n";
my $lineorig = $2;
my $line = $2;
# strip off leading 0x
$line =~ s/^0x//;
# merge chunks with spaces
$line =~ s/(\S)\s(\S)/$1$2/g;
my $linemerge = $line;
# strip off comments
$line =~ /^(\S*)/;
$payload = $1;
# if ($address >= 17520 && $address <= 17552) { # was 12304
# print "Address: $address\n orig: $lineorig \n merge: $linemerge \n line: $line \n payload: $payload\n";
# }
&emitData($address, $payload);
}
if (/Disassembly of section .riscv.attributes:/) { $mode = 2; }
}
}
close(FILE);
# print("maxaddress: $maxaddress\n");
$maxaddress += 32; # pad some zeros at the end
# print("maxaddress: $maxaddress\n");
# print to memory file
if ($fname =~ /rv32/) {
open(MEMFILE, ">$memfile") || die("Can't write $memfile");
for (my $i=0; $i<= $maxaddress; $i = $i + 4) {
for ($j=3; $j>=0; $j--) {
if (defined($memfilebytes[$i+$j])) {
print MEMFILE "$memfilebytes[$i+$j]";
} else {
print MEMFILE "00";
}
}
print MEMFILE "\n";
}
close(MEMFILE);
} else {
open(MEMFILE, ">$memfile") || die("Can't write $memfile");
for (my $i=0; $i<= $maxaddress; $i = $i + 8) {
for ($j=7; $j>=0; $j--) {
my $loc = $i+$j;
# if ($loc >= 17520 && $loc <= 17552) {
# print "loc: $loc val $memfilebytes[$loc]\n";
# }
if (defined($memfilebytes[$loc])) {
print MEMFILE "$memfilebytes[$loc]";
} else {
print MEMFILE "00";
}
}
print MEMFILE "\n";
}
close(MEMFILE);
}
}
}
print("\n");
sub emitData {
# print the data portion of the ELF into a memroy file, including 0s for empty stuff
# deal with endianness
my $address = shift;
my $payload = shift;
# if ($address > 17520 && $address < 17552) { # was 12304
# print("Emitting data. address = $address payload = $payload\n");
# }
my $len = length($payload);
if ($len <= 8) {
# print word or halfword
for(my $i=0; $i<$len/2; $i++) {
my $adr = $address+$i;
my $b = substr($payload, $len-2-2*$i, 2);
$memfilebytes[$adr] = $b;
# if ($address >= 17520 && $address <= 17552) {
# print(" Wrote $b to $adr\n");
# }
# print(" $adr $b\n");
}
} elsif ($len == 12) {
# weird case of three halfwords on line
&emitData($address, substr($payload, 0, 4));
&emitData($address+2, substr($payload, 4, 4));
&emitData($address+4, substr($payload, 8, 4));
} else {
&emitData($address, substr($payload, 0, 8));
&emitData($address+4, substr($payload, 8, $len-8));
}
}
sub fixadr {
# strip off leading 8 from address and convert to decimal
my $adr = shift;
if ($adr =~ s/^8/0/) { return hex($adr); }
else { die("address $adr lacks leading 8\n"); }
}

1
examples/verilog/fulladder/fulladder.tv
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@ -1,3 +1,4 @@
// abc_cout s
000_00 000_00
001_01 001_01
010_01 010_01

2
pipelined/src/ieu/extend.sv
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@ -46,7 +46,7 @@ module extend (
3'b100: ExtImmD = {{(`XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; 3'b100: ExtImmD = {{(`XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0};
// Store Conditional: zero offset // Store Conditional: zero offset
3'b101: if (`A_SUPPORTED) ExtImmD = 0; 3'b101: if (`A_SUPPORTED) ExtImmD = 0;
else ExtImmD = undefined; else ExtImmD = undefined;
default: ExtImmD = undefined; // undefined default: ExtImmD = undefined; // undefined
endcase endcase
endmodule endmodule

1
pipelined/src/ieu/forward.sv
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@ -57,5 +57,4 @@ module forward(
assign LoadStallD = (MemReadE|SCE) & MatchDE; assign LoadStallD = (MemReadE|SCE) & MatchDE;
assign MulDivStallD = MulDivE & MatchDE; assign MulDivStallD = MulDivE & MatchDE;
assign CSRRdStallD = CSRReadE & MatchDE; assign CSRRdStallD = CSRReadE & MatchDE;
endmodule endmodule

74
pipelined/src/ieu/ieu.sv
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@ -89,68 +89,26 @@ module ieu (
logic JumpE; logic JumpE;
controller c( controller c(
.clk, .reset, .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
// Decode stage control signals .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
.StallD, .FlushD, .InstrD, .ImmSrcD, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE,
.IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .Funct3E, .MulDivE, .W64E, .JumpE, .StallM, .FlushM, .MemRWM,
// Execute stage control signals .CSRReadM, .CSRWriteM, .PrivilegedM, .SCE, .AtomicE, .AtomicM, .Funct3M,
.StallE, .FlushE, .FlagsE, .FWriteIntE, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
.PCSrcE, // for datapath and Hazard Unit .StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWritePendingDEM, .StoreStallD);
.ALUControlE, .ALUSrcAE, .ALUSrcBE,
.ALUResultSrcE,
.MemReadE, .CSRReadE, // for Hazard Unit
.Funct3E, .MulDivE, .W64E,
.JumpE,
// Memory stage control signals
.StallM, .FlushM, .MemRWM,
.CSRReadM, .CSRWriteM, .PrivilegedM,
.SCE, .AtomicE, .AtomicM, .Funct3M,
.RegWriteM, // for Hazard Unit
.InvalidateICacheM, .FlushDCacheM, .InstrValidM,
.FWriteIntM,
// Writeback stage control signals
.StallW, .FlushW,
.RegWriteW, // for datapath and Hazard Unit
.ResultSrcW,
// Stall during CSRs
.CSRWritePendingDEM,
.StoreStallD
);
datapath dp( datapath dp(
.clk, .reset, .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
// Decode stage signals .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
.ImmSrcD, .InstrD, .FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
// Execute stage signals .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM,
.StallE, .FlushE, .ForwardAE, .ForwardBE, .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW,
.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .CSRReadValW, .ReadDataM, .MulDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
.ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
.FWriteDataE, .PCE, .PCLinkE, .FlagsE,
.IEUAdrE,
.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
// Memory stage signals
.StallM, .FlushM, .FWriteIntM, .FIntResM,
.SrcAM, .WriteDataM,
// Writeback stage signals
.StallW, .FlushW, .RegWriteW,
.SquashSCW, .ResultSrcW, .ReadDataW,
// input logic [`XLEN-1:0] PCLinkW,
.CSRReadValW, .ReadDataM, .MulDivResultW,
// Hazard Unit signals
.Rs1D, .Rs2D, .Rs1E, .Rs2E,
.RdE, .RdM, .RdW
);
forward fw( forward fw(
.Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
.MemReadE, .MulDivE, .CSRReadE, .MemReadE, .MulDivE, .CSRReadE, .RegWriteM, .RegWriteW,
.RegWriteM, .RegWriteW, .FWriteIntE, .SCE, .ForwardAE, .ForwardBE,
.FWriteIntE, .FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD);
.SCE,
// Forwarding controls
.ForwardAE, .ForwardBE,
.FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD
);
endmodule endmodule

2
pipelined/src/mmu/tlbcam.sv
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@ -57,7 +57,5 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
.WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches)); .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches));
assign CAMHit = |Matches & ~TLBFlush; assign CAMHit = |Matches & ~TLBFlush;
or_rows #(TLB_ENTRIES,2) PageTypeOr(PageTypeRead, HitPageType); or_rows #(TLB_ENTRIES,2) PageTypeOr(PageTypeRead, HitPageType);
//assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result
endmodule endmodule

3
pipelined/src/mmu/tlblru.sv
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@ -47,6 +47,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) (
assign RUBitsAccessed = AccessLines | RUBits; assign RUBitsAccessed = AccessLines | RUBits;
assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
// enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21
flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits); flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
// *** seems like enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21
endmodule endmodule

6
setup.sh
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@ -11,11 +11,11 @@ export RISCV=/opt/riscv # change this if you installed the tools in a differen
# Tools # Tools
# GCCZ # GCCZ
export LD_LIBRARY_PATH=$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib:$LD_LIBRARY_PATH export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH # GCC tools export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools
# Spike # Spike
export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH
export PATH=$RISCV/bin:$PATH export PATH=$PATH:$RISCV/bin
# exe2memfile # exe2memfile
export PATH=~/riscv-wally/bin:$PATH # exe2memfile; change this if riscv-wally isn't at your home directory export PATH=~/riscv-wally/bin:$PATH # exe2memfile; change this if riscv-wally isn't at your home directory
# Verilator # Verilator