diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99bd..307c77b26 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 diff --git a/bin/elf2hex.sh b/bin/elf2hex.sh index 15c8dd4cf..5808f4109 100755 --- a/bin/elf2hex.sh +++ b/bin/elf2hex.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # james.stine@okstate.edu 4 Jan 2022 # Script to run elf2hex for memfile for diff --git a/bin/exe2memfile-deleteme.pl b/bin/exe2memfile-deleteme.pl deleted file mode 100755 index 8c09583b1..000000000 --- a/bin/exe2memfile-deleteme.pl +++ /dev/null @@ -1,170 +0,0 @@ -#!/usr/bin/perl -w - -# exe2memfile.pl -# David_Harris@hmc.edu 26 November 2020 -# Converts an executable file to a series of 32-bit hex instructions -# to read into a Verilog simulation with $readmemh - -use File::stat; -use IO::Handle; - -if ($#ARGV == -1) { - die("Usage: $0 executable_file"); -} - -# array to hold contents of memory file -my $maxmemfilesize = 1000000; -my @memfilebytes = (0)*$maxmemfilesize*4; -my $maxaddress = 0; - -STDOUT->autoflush(1); -my $numfiles = $#ARGV+1; -if ($numfiles > 1) { - print ("Processing $numfiles memfiles: "); -} -my $frac = $#ARGV/10; -for(my $i=0; $i<=$#ARGV; $i++) { - if ($i > 0 && ($i < 10 || $i % $frac == 0)) { print ("$i ") }; - my $fname = $ARGV[$i]; -# print "fname = $fname"; - my $ofile = $fname.".objdump"; - my $memfile = $fname.".memfile"; - - my $needsprocessing = 0; - if (!-e $memfile) { $needsprocessing = 1; } # create memfile if it doesn't exist - else { - my $osb = stat($ofile) || die("Can't stat $ofile"); - my $msb = stat($memfile) || die("Can't stat $memfile"); - my $otime = $osb->mtime; - my $mtime = $msb->mtime; - if ($otime > $mtime) { $needsprocessing = 1; } # is memfile out of date? - } - - if ($needsprocessing == 1) { - open(FILE, $ofile) || die("Can't read $ofile"); - my $mode = 0; # parse for code - my $address; - - # initialize to all zeros; - for (my $i=0; $i < $maxmemfilesize*4; $i++) { - $memfilebytes[$i] = "00"; - } - - while() { - if ($mode == 0) { # Parse code - # print("Examining $_\n"); - if (/^\s*(\S\S\S\S\S\S\S\S):\s+(\S+)\s+/) { - $address = &fixadr($1); - my $instr = $2; - my $len = length($instr); - for (my $i=0; $i<$len/2; $i++) { - $memfilebytes[$address+$i] = substr($instr, $len-2-2*$i, 2); - } - # print ("address $address $instr\n"); - } - if (/Disassembly of section .data:/) { $mode = 1;} - } elsif ($mode == 1) { # Parse data segment -# if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) { # changed to \t 30 Oct 2021 dmh to fix parsing issue in d_fmadd_b17 - if (/^\s*(\S\S\S\S\S\S\S\S):\s+(.*)/) { - $address = &fixadr($1); - # print "addresss $address maxaddress $maxaddress\n"; - if ($address > $maxaddress) { $maxaddress = $address; } - #print "test $address $1 $2\n"; - my $lineorig = $2; - my $line = $2; - # strip off leading 0x - $line =~ s/^0x//; - # merge chunks with spaces - $line =~ s/(\S)\s(\S)/$1$2/g; - my $linemerge = $line; - # strip off comments - $line =~ /^(\S*)/; - $payload = $1; -# if ($address >= 17520 && $address <= 17552) { # was 12304 -# print "Address: $address\n orig: $lineorig \n merge: $linemerge \n line: $line \n payload: $payload\n"; -# } - &emitData($address, $payload); - } - if (/Disassembly of section .riscv.attributes:/) { $mode = 2; } - } - } - close(FILE); -# print("maxaddress: $maxaddress\n"); - $maxaddress += 32; # pad some zeros at the end -# print("maxaddress: $maxaddress\n"); - - # print to memory file - if ($fname =~ /rv32/) { - open(MEMFILE, ">$memfile") || die("Can't write $memfile"); - for (my $i=0; $i<= $maxaddress; $i = $i + 4) { - for ($j=3; $j>=0; $j--) { - if (defined($memfilebytes[$i+$j])) { - print MEMFILE "$memfilebytes[$i+$j]"; - } else { - print MEMFILE "00"; - } - } - print MEMFILE "\n"; - } - close(MEMFILE); - } else { - open(MEMFILE, ">$memfile") || die("Can't write $memfile"); - for (my $i=0; $i<= $maxaddress; $i = $i + 8) { - for ($j=7; $j>=0; $j--) { - my $loc = $i+$j; -# if ($loc >= 17520 && $loc <= 17552) { -# print "loc: $loc val $memfilebytes[$loc]\n"; -# } - if (defined($memfilebytes[$loc])) { - print MEMFILE "$memfilebytes[$loc]"; - } else { - print MEMFILE "00"; - } - } - print MEMFILE "\n"; - } - close(MEMFILE); - } - } -} -print("\n"); - -sub emitData { - # print the data portion of the ELF into a memroy file, including 0s for empty stuff - # deal with endianness - my $address = shift; - my $payload = shift; - -# if ($address > 17520 && $address < 17552) { # was 12304 -# print("Emitting data. address = $address payload = $payload\n"); -# } - - my $len = length($payload); - if ($len <= 8) { - # print word or halfword - for(my $i=0; $i<$len/2; $i++) { - my $adr = $address+$i; - my $b = substr($payload, $len-2-2*$i, 2); - $memfilebytes[$adr] = $b; -# if ($address >= 17520 && $address <= 17552) { -# print(" Wrote $b to $adr\n"); -# } -# print(" $adr $b\n"); - } - } elsif ($len == 12) { - # weird case of three halfwords on line - &emitData($address, substr($payload, 0, 4)); - &emitData($address+2, substr($payload, 4, 4)); - &emitData($address+4, substr($payload, 8, 4)); - } else { - &emitData($address, substr($payload, 0, 8)); - &emitData($address+4, substr($payload, 8, $len-8)); - } -} - -sub fixadr { - # strip off leading 8 from address and convert to decimal - my $adr = shift; - if ($adr =~ s/^8/0/) { return hex($adr); } - else { die("address $adr lacks leading 8\n"); } -} diff --git a/examples/verilog/fulladder/fulladder.tv b/examples/verilog/fulladder/fulladder.tv index 960acebb6..6e8f1dd6c 100644 --- a/examples/verilog/fulladder/fulladder.tv +++ b/examples/verilog/fulladder/fulladder.tv @@ -1,3 +1,4 @@ +// abc_cout s 000_00 001_01 010_01 diff --git a/pipelined/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv index 5372652b2..eed48e4df 100644 --- a/pipelined/src/ieu/extend.sv +++ b/pipelined/src/ieu/extend.sv @@ -46,7 +46,7 @@ module extend ( 3'b100: ExtImmD = {{(`XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; // Store Conditional: zero offset 3'b101: if (`A_SUPPORTED) ExtImmD = 0; - else ExtImmD = undefined; + else ExtImmD = undefined; default: ExtImmD = undefined; // undefined endcase endmodule diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv index d041f9437..f642e693d 100644 --- a/pipelined/src/ieu/forward.sv +++ b/pipelined/src/ieu/forward.sv @@ -57,5 +57,4 @@ module forward( assign LoadStallD = (MemReadE|SCE) & MatchDE; assign MulDivStallD = MulDivE & MatchDE; assign CSRRdStallD = CSRReadE & MatchDE; - endmodule diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index aabd87988..09d9c08e0 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -89,68 +89,26 @@ module ieu ( logic JumpE; controller c( - .clk, .reset, - // Decode stage control signals - .StallD, .FlushD, .InstrD, .ImmSrcD, - .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, - // Execute stage control signals - .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, // for datapath and Hazard Unit - .ALUControlE, .ALUSrcAE, .ALUSrcBE, - .ALUResultSrcE, - .MemReadE, .CSRReadE, // for Hazard Unit - .Funct3E, .MulDivE, .W64E, - .JumpE, - // Memory stage control signals - .StallM, .FlushM, .MemRWM, - .CSRReadM, .CSRWriteM, .PrivilegedM, - .SCE, .AtomicE, .AtomicM, .Funct3M, - .RegWriteM, // for Hazard Unit - .InvalidateICacheM, .FlushDCacheM, .InstrValidM, - .FWriteIntM, - // Writeback stage control signals - .StallW, .FlushW, - .RegWriteW, // for datapath and Hazard Unit - .ResultSrcW, - // Stall during CSRs - .CSRWritePendingDEM, - .StoreStallD - ); + .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, + .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, + .Funct3E, .MulDivE, .W64E, .JumpE, .StallM, .FlushM, .MemRWM, + .CSRReadM, .CSRWriteM, .PrivilegedM, .SCE, .AtomicE, .AtomicM, .Funct3M, + .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM, + .StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWritePendingDEM, .StoreStallD); datapath dp( - .clk, .reset, - // Decode stage signals - .ImmSrcD, .InstrD, - // Execute stage signals - .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, - .ALUResultSrcE, .JumpE, .IllegalFPUInstrE, - .FWriteDataE, .PCE, .PCLinkE, .FlagsE, - .IEUAdrE, - .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B - // Memory stage signals - .StallM, .FlushM, .FWriteIntM, .FIntResM, - .SrcAM, .WriteDataM, - // Writeback stage signals - .StallW, .FlushW, .RegWriteW, - .SquashSCW, .ResultSrcW, .ReadDataW, - // input logic [`XLEN-1:0] PCLinkW, - .CSRReadValW, .ReadDataM, .MulDivResultW, - // Hazard Unit signals - .Rs1D, .Rs2D, .Rs1E, .Rs2E, - .RdE, .RdM, .RdW - ); + .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, + .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE, + .FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, + .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, + .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, + .CSRReadValW, .ReadDataM, .MulDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); forward fw( .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, - .MemReadE, .MulDivE, .CSRReadE, - .RegWriteM, .RegWriteW, - .FWriteIntE, - .SCE, - // Forwarding controls - .ForwardAE, .ForwardBE, - .FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD - ); - + .MemReadE, .MulDivE, .CSRReadE, .RegWriteM, .RegWriteW, + .FWriteIntE, .SCE, .ForwardAE, .ForwardBE, + .FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD); endmodule diff --git a/pipelined/src/mmu/tlbcam.sv b/pipelined/src/mmu/tlbcam.sv index 5068972a6..392e8e7a3 100644 --- a/pipelined/src/mmu/tlbcam.sv +++ b/pipelined/src/mmu/tlbcam.sv @@ -57,7 +57,5 @@ module tlbcam #(parameter TLB_ENTRIES = 8, .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches)); assign CAMHit = |Matches & ~TLBFlush; or_rows #(TLB_ENTRIES,2) PageTypeOr(PageTypeRead, HitPageType); - //assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result - endmodule diff --git a/pipelined/src/mmu/tlblru.sv b/pipelined/src/mmu/tlblru.sv index 0223c214b..c755c602f 100644 --- a/pipelined/src/mmu/tlblru.sv +++ b/pipelined/src/mmu/tlblru.sv @@ -47,6 +47,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( assign RUBitsAccessed = AccessLines | RUBits; assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; + + // enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21 flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits); - // *** seems like enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21 endmodule diff --git a/setup.sh b/setup.sh index 1ebf52314..9c285415f 100755 --- a/setup.sh +++ b/setup.sh @@ -11,11 +11,11 @@ export RISCV=/opt/riscv # change this if you installed the tools in a differen # Tools # GCCZ -export LD_LIBRARY_PATH=$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib:$LD_LIBRARY_PATH -export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH # GCC tools +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib +export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools # Spike export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH -export PATH=$RISCV/bin:$PATH +export PATH=$PATH:$RISCV/bin # exe2memfile export PATH=~/riscv-wally/bin:$PATH # exe2memfile; change this if riscv-wally isn't at your home directory # Verilator