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cturek 2022-07-08 21:53:52 +00:00
parent 5c14c97e49
commit 0dc30a0acf
2 changed files with 31 additions and 37 deletions
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43
pipelined/srt/srt.sv
View File

@ -93,11 +93,7 @@ module srt (
otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot); otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
<<<<<<< Updated upstream
expcalc expcalc(.XExp, .YExp, .calcExp);
=======
expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt); expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt);
>>>>>>> Stashed changes
signcalc signcalc(.XSign, .YSign, .calcSign); signcalc signcalc(.XSign, .YSign, .calcSign);
endmodule endmodule
@ -187,6 +183,26 @@ module qsel2 ( // *** eventually just change to 4 bits
assign #1 qm = magnitude & sign; assign #1 qm = magnitude & sign;
endmodule endmodule
////////////////////////////////////
// Adder Input Selection, Radix 2 //
////////////////////////////////////
module fsel2 (
input logic sp, sn,
input logic [`DIVLEN+3:0] C, S, SM,
output logic [`DIVLEN+3:0] F
);
logic [`DIVLEN+3:0] FP, FN;
// Generate for both positive and negative bits
assign FP = ~S & C;
assign FN = SM | (C & (~C << 2));
// Choose which adder input will be used
assign F = sp ? FP : (sn ? FN : (`DIVLEN+4){1'b0});
endmodule
/////////////////////////////////// ///////////////////////////////////
// On-The-Fly Converter, Radix 2 // // On-The-Fly Converter, Radix 2 //
/////////////////////////////////// ///////////////////////////////////
@ -234,6 +250,17 @@ module otfc2 #(parameter N=64) (
endmodule endmodule
///////////////////////////////
// Square Root OTFC, Radix 2 //
///////////////////////////////
module softc2(
input logic clk,
input logic Start,
input logic sp, sn,
output logic S,
);
endmodule
///////////// /////////////
// counter // // counter //
///////////// /////////////
@ -301,13 +328,6 @@ endmodule
// expcalc // // expcalc //
////////////// //////////////
module expcalc( module expcalc(
<<<<<<< Updated upstream
input logic [`NE-1:0] XExp, YExp,
output logic [`NE-1:0] calcExp
);
assign calcExp = XExp - YExp + (`NE)'(`BIAS);
=======
input logic [`NE-1:0] XExp, YExp, input logic [`NE-1:0] XExp, YExp,
input logic Sqrt, input logic Sqrt,
output logic [`NE-1:0] calcExp output logic [`NE-1:0] calcExp
@ -317,7 +337,6 @@ module expcalc(
assign SExp = {1'b0, SXExp[`NE-1:1]} + (`NE)'(`BIAS); assign SExp = {1'b0, SXExp[`NE-1:1]} + (`NE)'(`BIAS);
assign DExp = XExp - YExp + (`NE)'(`BIAS); assign DExp = XExp - YExp + (`NE)'(`BIAS);
assign calcExp = Sqrt ? SExp : DExp; assign calcExp = Sqrt ? SExp : DExp;
>>>>>>> Stashed changes
endmodule endmodule

25
pipelined/srt/testbench.sv
View File

@ -62,11 +62,6 @@ module testbench;
// `define mema 255:192 // `define mema 255:192
// FLOAT TEST SIZES // FLOAT TEST SIZES
<<<<<<< Updated upstream
`define memr 63:0
`define memb 127:64
`define mema 191:128
=======
// `define memr 63:0 // `define memr 63:0
// `define memb 127:64 // `define memb 127:64
// `define mema 191:128 // `define mema 191:128
@ -75,7 +70,6 @@ module testbench;
`define memr 63:0 `define memr 63:0
`define mema 127:64 `define mema 127:64
`define memb 191:128 `define memb 191:128
>>>>>>> Stashed changes
// Test logicisters // Test logicisters
logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file
@ -86,13 +80,9 @@ module testbench;
logic rsign; logic rsign;
integer testnum, errors; integer testnum, errors;
<<<<<<< Updated upstream
assign Int = 1'b0;
=======
// Equip Int test or Sqrt test // Equip Int test or Sqrt test
assign Int = 1'b0; assign Int = 1'b0;
assign Sqrt = 1'b1; assign Sqrt = 1'b1;
>>>>>>> Stashed changes
// Divider // Divider
srt srt(.clk, .Start(req), srt srt(.clk, .Start(req),
@ -101,11 +91,7 @@ module testbench;
.XSign(asign), .YSign(bsign), .rsign, .XSign(asign), .YSign(bsign), .rsign,
.SrcXFrac(afrac), .SrcYFrac(bfrac), .SrcXFrac(afrac), .SrcYFrac(bfrac),
.SrcA(a), .SrcB(b), .Fmt(2'b00), .SrcA(a), .SrcB(b), .Fmt(2'b00),
<<<<<<< Updated upstream
.W64(1'b1), .Signed(1'b0), .Int, .Sqrt(1'b0),
=======
.W64(1'b1), .Signed(1'b0), .Int, .Sqrt, .W64(1'b1), .Signed(1'b0), .Int, .Sqrt,
>>>>>>> Stashed changes
.Quot, .Rem(), .Flags(), .done); .Quot, .Rem(), .Flags(), .done);
// Counter // Counter
@ -125,11 +111,7 @@ module testbench;
begin begin
testnum = 0; testnum = 0;
errors = 0; errors = 0;
<<<<<<< Updated upstream
$readmemh ("testvectors", Tests);
=======
$readmemh ("sqrttestvectors", Tests); $readmemh ("sqrttestvectors", Tests);
>>>>>>> Stashed changes
Vec = Tests[testnum]; Vec = Tests[testnum];
a = Vec[`mema]; a = Vec[`mema];
{asign, aExp, afrac} = a; {asign, aExp, afrac} = a;
@ -183,17 +165,10 @@ module testbench;
req <= #5 1; req <= #5 1;
diffp = correctr[51:0] - r; diffp = correctr[51:0] - r;
diffn = r - correctr[51:0]; diffn = r - correctr[51:0];
<<<<<<< Updated upstream
if (($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
begin
errors = errors + 1;
$display("result was %h, should be %h %h %h\n", rSqrt, correctr, diffn, diffp);
=======
if (rExp !== correctr[62:52]) // check if accurate to 1 ulp if (rExp !== correctr[62:52]) // check if accurate to 1 ulp
begin begin
errors = errors + 1; errors = errors + 1;
$display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
>>>>>>> Stashed changes
$display("failed\n"); $display("failed\n");
$stop; $stop;
end end