From 0dc30a0acf5522baede575c33ef8c1a61f5337da Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Fri, 8 Jul 2022 21:53:52 +0000
Subject: [PATCH] F Selection

---
 pipelined/srt/srt.sv       | 43 +++++++++++++++++++++++++++-----------
 pipelined/srt/testbench.sv | 25 ----------------------
 2 files changed, 31 insertions(+), 37 deletions(-)

diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv
index a980511ff..6e8cd5601 100644
--- a/pipelined/srt/srt.sv
+++ b/pipelined/srt/srt.sv
@@ -93,11 +93,7 @@ module srt (
   
   otfc2  #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
 
-<<<<<<< Updated upstream
-  expcalc expcalc(.XExp, .YExp, .calcExp);
-=======
   expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt);
->>>>>>> Stashed changes
 
   signcalc signcalc(.XSign, .YSign, .calcSign);
 endmodule
@@ -187,6 +183,26 @@ module qsel2 ( // *** eventually just change to 4 bits
   assign #1 qm = magnitude & sign;
 endmodule
 
+////////////////////////////////////
+// Adder Input Selection, Radix 2 //
+////////////////////////////////////
+module fsel2 (
+  input  logic sp, sn,
+  input  logic [`DIVLEN+3:0] C, S, SM,
+  output logic [`DIVLEN+3:0] F
+);
+  logic [`DIVLEN+3:0] FP, FN;
+  
+  // Generate for both positive and negative bits
+  assign FP = ~S & C;
+  assign FN = SM | (C & (~C << 2));
+
+  // Choose which adder input will be used
+
+  assign F = sp ? FP : (sn ? FN : (`DIVLEN+4){1'b0});
+
+endmodule
+
 ///////////////////////////////////
 // On-The-Fly Converter, Radix 2 //
 ///////////////////////////////////
@@ -234,6 +250,17 @@ module otfc2 #(parameter N=64) (
 
 endmodule
 
+///////////////////////////////
+// Square Root OTFC, Radix 2 //
+///////////////////////////////
+module softc2(
+  input  logic clk,
+  input  logic Start,
+  input  logic sp, sn,
+  output logic S,
+);
+
+endmodule
 /////////////
 // counter //
 /////////////
@@ -301,13 +328,6 @@ endmodule
 // expcalc  //
 //////////////
 module expcalc(
-<<<<<<< Updated upstream
-  input logic  [`NE-1:0] XExp, YExp,
-  output logic [`NE-1:0] calcExp
-);
-
-  assign calcExp = XExp - YExp + (`NE)'(`BIAS);
-=======
   input  logic [`NE-1:0] XExp, YExp,
   input  logic           Sqrt,
   output logic [`NE-1:0] calcExp
@@ -317,7 +337,6 @@ module expcalc(
   assign SExp  = {1'b0, SXExp[`NE-1:1]} + (`NE)'(`BIAS);
   assign DExp  = XExp - YExp + (`NE)'(`BIAS);
   assign calcExp = Sqrt ? SExp : DExp;
->>>>>>> Stashed changes
 
 endmodule
 
diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv
index 985d0ad75..83f337073 100644
--- a/pipelined/srt/testbench.sv
+++ b/pipelined/srt/testbench.sv
@@ -62,11 +62,6 @@ module testbench;
   // `define mema  255:192
 
   // FLOAT TEST SIZES
-<<<<<<< Updated upstream
-  `define memr  63:0 
-  `define memb  127:64
-  `define mema  191:128
-=======
   // `define memr  63:0 
   // `define memb  127:64
   // `define mema  191:128
@@ -75,7 +70,6 @@ module testbench;
   `define memr  63:0 
   `define mema  127:64
   `define memb  191:128
->>>>>>> Stashed changes
 
   // Test logicisters
   logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE];  // Space for input file
@@ -86,13 +80,9 @@ module testbench;
   logic        rsign;
   integer testnum, errors;
 
-<<<<<<< Updated upstream
-  assign Int = 1'b0;
-=======
   // Equip Int test or Sqrt test
   assign Int = 1'b0;
   assign Sqrt = 1'b1;
->>>>>>> Stashed changes
 
   // Divider
   srt srt(.clk, .Start(req), 
@@ -101,11 +91,7 @@ module testbench;
                 .XSign(asign), .YSign(bsign), .rsign,
                 .SrcXFrac(afrac), .SrcYFrac(bfrac), 
                 .SrcA(a), .SrcB(b), .Fmt(2'b00), 
-<<<<<<< Updated upstream
-                .W64(1'b1), .Signed(1'b0), .Int, .Sqrt(1'b0), 
-=======
                 .W64(1'b1), .Signed(1'b0), .Int, .Sqrt, 
->>>>>>> Stashed changes
                 .Quot, .Rem(), .Flags(), .done);
 
   // Counter
@@ -125,11 +111,7 @@ module testbench;
     begin
       testnum = 0; 
       errors = 0;
-<<<<<<< Updated upstream
-      $readmemh ("testvectors", Tests);
-=======
       $readmemh ("sqrttestvectors", Tests);
->>>>>>> Stashed changes
       Vec = Tests[testnum];
       a = Vec[`mema];
       {asign, aExp, afrac} = a;
@@ -183,17 +165,10 @@ module testbench;
         req <= #5 1;
         diffp = correctr[51:0] - r;
         diffn = r - correctr[51:0];
-<<<<<<< Updated upstream
-        if (($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp
-          begin
-            errors = errors + 1;
-            $display("result was %h, should be %h %h %h\n", rSqrt, correctr, diffn, diffp);
-=======
         if (rExp !== correctr[62:52]) // check if accurate to 1 ulp
           begin
             errors = errors + 1;
             $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp);
->>>>>>> Stashed changes
             $display("failed\n");
             $stop;
           end