diff --git a/bin/CacheSim.py b/bin/CacheSim.py
index d07ded9ea..f66cb95d0 100755
--- a/bin/CacheSim.py
+++ b/bin/CacheSim.py
@@ -84,6 +84,14 @@ class Cache:
         for way in self.ways:
             for line in way:
                 line.dirty = False
+
+    # invalidate this specific line
+    def cboinvalidate(self, addr):
+        tag, setnum, _ = self.splitaddr(addr)
+        for waynum in range(self.numways):
+            line = self.ways[waynum][setnum]
+            if line.tag == tag and line.valid:
+                line.dirty = 0
     
     # invalidates the cache by setting all valid bits to False
     def invalidate(self):
@@ -108,14 +116,15 @@ class Cache:
     # performs a cache access with the given address.
     # returns a character representing the outcome:
     # H/M/E/D - hit, miss, eviction, or eviction with writeback
-    def cacheaccess(self, addr, write=False):
+    def cacheaccess(self, addr, write=False, clean=False):
         tag, setnum, _ = self.splitaddr(addr)
 
         # check our ways to see if we have a hit
+        #print(f"addr is {addr:x} Set is {setnum}")
         for waynum in range(self.numways):
             line = self.ways[waynum][setnum]
             if line.tag == tag and line.valid:
-                line.dirty = line.dirty or write
+                line.dirty = 0 if clean else line.dirty or write
                 self.update_pLRU(waynum, setnum)
                 return 'H'
 
@@ -132,6 +141,7 @@ class Cache:
         
         # we need to evict. Select a victim and overwrite.
         victim = self.getvictimway(setnum)
+        #print(f"addr is {addr:x} Victim is {victim} Set is {setnum}")
         line = self.ways[victim][setnum]
         prevdirty = line.dirty
         line.tag = tag
@@ -243,10 +253,15 @@ def main():
                     cache.invalidate()
                     if args.verbose:
                         print("I")
+                elif lninfo[1] == 'C' or lninfo[1] == 'L':
+                    cache.cboinvalidate()
+                    if args.verbose:
+                        print("C");
                 else:
                     addr = int(lninfo[0], 16)
-                    iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
-                    result = cache.cacheaccess(addr, iswrite)
+                    iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' or lninfo[1] == 'Z'
+                    iscboclean = lninfo[1] == 'C'
+                    result = cache.cacheaccess(addr, iswrite, iscboclean)
                     
                     if args.verbose:
                         tag, setnum, offset = cache.splitaddr(addr)
diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv
index 6b026257a..619cd13d5 100644
--- a/testbench/common/loggers.sv
+++ b/testbench/common/loggers.sv
@@ -210,6 +210,10 @@ module loggers import cvw::*; #(parameter cvw_t P,
                          dut.core.lsu.LSUAtomicM[1] ? "A" :
                          dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
                          dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
+                         dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" :   // cmo.zero
+                         dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" :   // cmo.inval should just clear the valid and dirty bits
+                         dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" :   // cmo.clean should act like a read in terms of the lru, but clears the dirty bit
+                         dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" :   // cmo.flush should just clear and the valid and drity bits
                          "NULL";
     end