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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2022-11-13 04:23:26 -08:00
commit 0ce3cc393a
4 changed files with 10 additions and 8 deletions
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2
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -74,7 +74,7 @@ module fdivsqrt(
fdivsqrtfsm fdivsqrtfsm( fdivsqrtfsm fdivsqrtfsm(
.clk, .reset, .FmtE, .XsE, .SqrtE, .clk, .reset, .FmtE, .XsE, .SqrtE,
.DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
.XNaNE, .YNaNE, .XNaNE, .YNaNE, .MDUE, .n,
.XInfE, .YInfE, .WZero, .SpecialCaseM); .XInfE, .YInfE, .WZero, .SpecialCaseM);
fdivsqrtiter fdivsqrtiter( fdivsqrtiter fdivsqrtiter(
.clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,

4
pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
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@ -43,6 +43,8 @@ module fdivsqrtfsm(
input logic StallE, input logic StallE,
input logic StallM, input logic StallM,
input logic WZero, input logic WZero,
input logic MDUE,
input logic [`DIVBLEN:0] n,
output logic DivDone, output logic DivDone,
output logic DivBusy, output logic DivBusy,
output logic SpecialCaseM output logic SpecialCaseM
@ -93,7 +95,7 @@ module fdivsqrtfsm(
always_comb begin always_comb begin
if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); cycles = MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
end end
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */

4
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -67,8 +67,8 @@ module fdivsqrtpreproc (
// ***can probably merge X LZC with conversion // ***can probably merge X LZC with conversion
// cout the number of leading zeros // cout the number of leading zeros
assign As = ForwardedSrcAE[`XLEN-1] & Funct3E[0]; assign As = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0];
assign Bs = ForwardedSrcBE[`XLEN-1] & Funct3E[0]; assign Bs = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0];
assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE; assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE; assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;

6
pipelined/testbench/tests.vh
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@ -1403,12 +1403,12 @@ string imperas32f[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/M/src/div-01.S", "rv32i_m/M/src/div-01.S",
"rv32i_m/M/src/divu-01.S", "rv32i_m/M/src/divu-01.S",
"rv32i_m/M/src/rem-01.S",
"rv32i_m/M/src/remu-01.S",
"rv32i_m/M/src/mul-01.S", "rv32i_m/M/src/mul-01.S",
"rv32i_m/M/src/mulh-01.S", "rv32i_m/M/src/mulh-01.S",
"rv32i_m/M/src/mulhsu-01.S", "rv32i_m/M/src/mulhsu-01.S",
"rv32i_m/M/src/mulhu-01.S", "rv32i_m/M/src/mulhu-01.S"
"rv32i_m/M/src/rem-01.S",
"rv32i_m/M/src/remu-01.S"
}; };
string arch32f[] = '{ string arch32f[] = '{