From e7c25f9562c4be9c8c02b1c2434516535b3f26cf Mon Sep 17 00:00:00 2001 From: cturek Date: Wed, 9 Nov 2022 18:41:26 +0000 Subject: [PATCH 1/3] Fixed asign and bsign --- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 756c5cc9f..b3d81705c 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -67,8 +67,8 @@ module fdivsqrtpreproc ( // ***can probably merge X LZC with conversion // cout the number of leading zeros - assign As = ForwardedSrcAE[`XLEN-1] & Funct3E[0]; - assign Bs = ForwardedSrcBE[`XLEN-1] & Funct3E[0]; + assign As = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0]; + assign Bs = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0]; assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE; assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE; From d5c5450f8d6a7215e6c3be48820e9a97e23e5aa6 Mon Sep 17 00:00:00 2001 From: cturek Date: Wed, 9 Nov 2022 18:42:00 +0000 Subject: [PATCH 2/3] Reoredered tests for arch32m --- pipelined/testbench/tests.vh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 633ecb81d..8ba3ed2fe 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1403,12 +1403,12 @@ string imperas32f[] = '{ `RISCVARCHTEST, "rv32i_m/M/src/div-01.S", "rv32i_m/M/src/divu-01.S", + "rv32i_m/M/src/rem-01.S", + "rv32i_m/M/src/remu-01.S", "rv32i_m/M/src/mul-01.S", "rv32i_m/M/src/mulh-01.S", "rv32i_m/M/src/mulhsu-01.S", - "rv32i_m/M/src/mulhu-01.S", - "rv32i_m/M/src/rem-01.S", - "rv32i_m/M/src/remu-01.S" + "rv32i_m/M/src/mulhu-01.S" }; string arch32f[] = '{ From ff410cd849f3f1374a53b6c8a511e97d877d0cd5 Mon Sep 17 00:00:00 2001 From: cturek Date: Fri, 11 Nov 2022 00:23:25 +0000 Subject: [PATCH 3/3] Added integer step counter to fsm --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 3f9c7e8a5..65ea6cc54 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -74,7 +74,7 @@ module fdivsqrt( fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, .DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, - .XNaNE, .YNaNE, + .XNaNE, .YNaNE, .MDUE, .n, .XInfE, .YInfE, .WZero, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8dc188c6b..94a19ed3a 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -42,7 +42,9 @@ module fdivsqrtfsm( input logic SqrtE, input logic StallE, input logic StallM, - input logic WZero, + input logic WZero, + input logic MDUE, + input logic [`DIVBLEN:0] n, output logic DivDone, output logic DivBusy, output logic SpecialCaseM @@ -93,7 +95,7 @@ module fdivsqrtfsm( always_comb begin if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); + cycles = MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); end /* verilator lint_on WIDTH */