mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw into fcov_makefile
This commit is contained in:
Jordan Carlin
commit
0caf18f3f3
@ -1 +1 @@
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Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401
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Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca
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@ -301,7 +301,8 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode):
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for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)):
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for file in filenames:
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# fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
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if (file.endswith(".elf") and fcovMode == 0 or file.endswith("ALL.elf") and fcovMode == 1):
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if ((file.endswith(".elf") and (fcovMode == 0 or "tests/priv" in dir)) or
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(file.endswith("ALL.elf") and fcovMode == 1)):
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fullfile = os.path.join(dirpath, file)
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fields = fullfile.rsplit('/', 3)
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if (fields[2] == "ref"):
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@ -419,9 +420,11 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
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addTests(tests64gc_nofp, coveragesim)
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if (args.fp):
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addTests(tests64gc_fp, coveragesim)
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elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
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elif (args.fcov): # run tests in lockstep in functional coverage mode
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, 1)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, 1)
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#addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)
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else:
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@ -436,6 +439,7 @@ else:
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if (args.nightly):
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addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0)
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addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0)
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addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 0)
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addTests(derivconfigtests, defaultsim)
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# addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script.
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@ -33,5 +33,6 @@
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// Privileged extensions
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`include "ZicsrM_coverage.svh"
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`include "ZicsrF_coverage.svh"
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`include "ZicsrU_coverage.svh"
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`include "RV32VM_coverage.svh"
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`include "RV32VM_PMP_coverage.svh"
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@ -36,7 +36,7 @@
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--override cpu/Zicboz=T
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--override cmomp_bytes=64 # Zic64b
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--override cmoz_bytes=64 # Zic64b
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--override lr_sc_grain=8 # Za64rs requires <=64; we use native word size
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--override lr_sc_grain=4 # Za64rs requires <=64; we use native word size
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# 64 KiB continuous huge pages supported
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#--override cpu/Svpbmt=F
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@ -34,6 +34,7 @@
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`include "RV64VM_coverage.svh"
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`include "ZicsrM_coverage.svh"
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`include "ZicsrF_coverage.svh"
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`include "ZicsrU_coverage.svh"
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// `include "RV64VM_PMP_coverage.svh"
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// `include "RV64CBO_VM_coverage.svh"
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// `include "RV64CBO_PMP_coverage.svh"
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@ -115,7 +115,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) (
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always_ff @(posedge PCLK)
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if (~PRESETn) begin
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MSIP <= 1'b0;
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MTIMECMP <= '0;
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MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
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end else if (memwrite) begin
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if (entry == 16'h0000) MSIP <= PWDATA[0];
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if (entry == 16'h4000)
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@ -175,6 +175,7 @@ module testbench;
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"arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd;
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"arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne;
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"arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh;
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"arch64pmp": if (P.PMP_ENTRIES > 0) tests = arch64pmp;
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endcase
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end else begin // RV32
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case (TEST)
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@ -217,6 +218,8 @@ module testbench;
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"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
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"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
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"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
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"arch32pmp": if (P.PMP_ENTRIES > 0) tests = arch32pmp;
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"arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32;
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endcase
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end
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if (tests.size() == 0 & ElfFile == "none") begin
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@ -149,6 +149,121 @@ string wally32a_lrsc[] = '{
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"rv32i_m/privilege/src/WALLY-lrsc-01.S"
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};
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string arch32pmp[] = '{
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`RISCVARCHTEST,
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"rv32i_m/pmp32/src/pmp-CFG-reg.S",
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"rv32i_m/pmp32/src/pmp-CSR-access.S",
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"rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-NA4-R-priority.S",
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"rv32i_m/pmp32/src/pmp-NA4-R.S",
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"rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-NA4-RW-priority.S",
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"rv32i_m/pmp32/src/pmp-NA4-RW.S",
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"rv32i_m/pmp32/src/pmp-NA4-RWX.S",
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"rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-NA4-RX-priority.S",
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"rv32i_m/pmp32/src/pmp-NA4-RX.S",
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"rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-NA4-X-priority.S",
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"rv32i_m/pmp32/src/pmp-NA4-X.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-R.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-RW.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-RWX.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-RX.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S",
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"rv32i_m/pmp32/src/pmp-NAPOT-X.S",
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"rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-TOR-R-priority.S",
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"rv32i_m/pmp32/src/pmp-TOR-R.S",
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"rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S",
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"rv32i_m/pmp32/src/pmp-TOR-RW-priority.S",
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"rv32i_m/pmp32/src/pmp-TOR-RW.S",
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"rv32i_m/pmp32/src/pmp-TOR-RWX.S",
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"rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-TOR-RX-priority.S",
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"rv32i_m/pmp32/src/pmp-TOR-RX.S",
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"rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S",
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"rv32i_m/pmp32/src/pmp-TOR-X-priority.S",
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"rv32i_m/pmp32/src/pmp-TOR-X.S"
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};
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string arch64pmp[] = '{
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`RISCVARCHTEST,
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"rv64i_m/pmp64/pmp64-CFG-reg.S",
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"rv64i_m/pmp64/pmp64-CSR-access.S",
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"rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-NA4-R-priority.S",
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"rv64i_m/pmp64/pmp64-NA4-R.S",
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"rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-NA4-RW-priority.S",
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"rv64i_m/pmp64/pmp64-NA4-RW.S",
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"rv64i_m/pmp64/pmp64-NA4-RWX.S",
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"rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-NA4-RX-priority.S",
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"rv64i_m/pmp64/pmp64-NA4-RX.S",
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"rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-NA4-X-priority.S",
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"rv64i_m/pmp64/pmp64-NA4-X.S",
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"rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-NAPOT-R-priority.S",
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"rv64i_m/pmp64/pmp64-NAPOT-R.S",
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"rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S",
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"rv64i_m/pmp64/pmp64-NAPOT-RW.S",
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"rv64i_m/pmp64/pmp64-NAPOT-RWX.S",
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"rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S",
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"rv64i_m/pmp64/pmp64-NAPOT-RX.S",
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"rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-NAPOT-X-priority.S",
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"rv64i_m/pmp64/pmp64-NAPOT-X.S",
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"rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-TOR-R-priority.S",
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"rv64i_m/pmp64/pmp64-TOR-R.S",
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"rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S",
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"rv64i_m/pmp64/pmp64-TOR-RW-priority.S",
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"rv64i_m/pmp64/pmp64-TOR-RW.S",
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"rv64i_m/pmp64/pmp64-TOR-RWX.S",
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"rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-TOR-RX-priority.S",
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"rv64i_m/pmp64/pmp64-TOR-RX.S",
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"rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S",
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"rv64i_m/pmp64/pmp64-TOR-X-priority.S",
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"rv64i_m/pmp64/pmp64-TOR-X.S"
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};
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string arch32vm_sv32[] = '{
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`RISCVARCHTEST,
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"rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S",
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"rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S",
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"rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S",
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"rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S",
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"rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
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"rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
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"rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S",
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"rv32i_m/vm_sv32/src/vm_mxr_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_mxr_U_mode.S",
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"rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S",
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"rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S",
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"rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
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"rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S",
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"rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S"
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};
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string arch64priv[] = '{
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`RISCVARCHTEST,
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"rv64i_m/privilege/src/ebreak.S",
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@ -52,7 +52,7 @@ class sail_cSim(pluginTemplate):
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ispec = utils.load_yaml(isa_yaml)['hart0']
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self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
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self.isa = 'rv' + self.xlen
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self.sailargs = ' '
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self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration
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self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
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if "I" in ispec["ISA"]:
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self.isa += 'i'
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@ -103,7 +103,6 @@ class sail_cSim(pluginTemplate):
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execute = "@cd "+testentry['work_dir']+";"
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# cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf
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cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf
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compile_cmd = cmd + ' -D' + " -D".join(testentry['macros'])
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execute+=compile_cmd+";"
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@ -117,8 +116,7 @@ class sail_cSim(pluginTemplate):
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reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
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execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying
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else:
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execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
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# execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
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execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
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cov_str = ' '
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for label in testentry['coverage_labels']:
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@ -26,4 +26,4 @@ hart0:
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legal:
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- extensions[25:0] bitmask [0x000112D, 0x0000000]
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wr_illegal:
|
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- Unchangedcd
|
||||
- Unchanged
|
||||
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