diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 3843c736e..a079bb263 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 3843c736e427a2b52a0d06e6220b073afa4be401 +Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca diff --git a/bin/regression-wally b/bin/regression-wally index c5b9c8f33..9a2d29201 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -301,7 +301,8 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode): for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)): for file in filenames: # fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files - if (file.endswith(".elf") and fcovMode == 0 or file.endswith("ALL.elf") and fcovMode == 1): + if ((file.endswith(".elf") and (fcovMode == 0 or "tests/priv" in dir)) or + (file.endswith("ALL.elf") and fcovMode == 1)): fullfile = os.path.join(dirpath, file) fields = fullfile.rsplit('/', 3) if (fields[2] == "ref"): @@ -419,9 +420,11 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode addTests(tests64gc_nofp, coveragesim) if (args.fp): addTests(tests64gc_fp, coveragesim) -elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode +elif (args.fcov): # run tests in lockstep in functional coverage mode addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1) addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1) + addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, 1) + addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, 1) #addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0) else: @@ -436,6 +439,7 @@ else: if (args.nightly): addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", lockstepsim, 0) addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", lockstepsim, 0) + addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv32i_m", "rv32gc", lockstepsim, 0) addTests(derivconfigtests, defaultsim) # addTests(bpredtests, defaultsim) # This is currently broken in regression due to something related to the new wsim script. diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh index ba876f6b7..afd34306e 100644 --- a/config/rv32gc/coverage.svh +++ b/config/rv32gc/coverage.svh @@ -33,5 +33,6 @@ // Privileged extensions `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" +`include "ZicsrU_coverage.svh" `include "RV32VM_coverage.svh" `include "RV32VM_PMP_coverage.svh" diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 46d0d31c3..2ba3c1280 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -36,7 +36,7 @@ --override cpu/Zicboz=T --override cmomp_bytes=64 # Zic64b --override cmoz_bytes=64 # Zic64b ---override lr_sc_grain=8 # Za64rs requires <=64; we use native word size +--override lr_sc_grain=4 # Za64rs requires <=64; we use native word size # 64 KiB continuous huge pages supported #--override cpu/Svpbmt=F diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index 901616311..6108376f9 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -34,6 +34,7 @@ `include "RV64VM_coverage.svh" `include "ZicsrM_coverage.svh" `include "ZicsrF_coverage.svh" +`include "ZicsrU_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv index 76735aaa6..e03745194 100644 --- a/src/uncore/clint_apb.sv +++ b/src/uncore/clint_apb.sv @@ -115,7 +115,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) ( always_ff @(posedge PCLK) if (~PRESETn) begin MSIP <= 1'b0; - MTIMECMP <= '0; + MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts end else if (memwrite) begin if (entry == 16'h0000) MSIP <= PWDATA[0]; if (entry == 16'h4000) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 7c28ebfe6..5b18d0bcf 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -175,6 +175,7 @@ module testbench; "arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd; "arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne; "arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh; + "arch64pmp": if (P.PMP_ENTRIES > 0) tests = arch64pmp; endcase end else begin // RV32 case (TEST) @@ -217,6 +218,8 @@ module testbench; "arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd; "arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne; "arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh; + "arch32pmp": if (P.PMP_ENTRIES > 0) tests = arch32pmp; + "arch32vm_sv32": if (P.VIRTMEM_SUPPORTED) tests = arch32vm_sv32; endcase end if (tests.size() == 0 & ElfFile == "none") begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 2b8d3a2ec..59cd84437 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -149,6 +149,121 @@ string wally32a_lrsc[] = '{ "rv32i_m/privilege/src/WALLY-lrsc-01.S" }; +string arch32pmp[] = '{ + `RISCVARCHTEST, + "rv32i_m/pmp32/src/pmp-CFG-reg.S", + "rv32i_m/pmp32/src/pmp-CSR-access.S", + "rv32i_m/pmp32/src/pmp-NA4-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-R-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-R.S", + "rv32i_m/pmp32/src/pmp-NA4-RW-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-RW-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-RW.S", + "rv32i_m/pmp32/src/pmp-NA4-RWX.S", + "rv32i_m/pmp32/src/pmp-NA4-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-RX-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-RX.S", + "rv32i_m/pmp32/src/pmp-NA4-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NA4-X-priority.S", + "rv32i_m/pmp32/src/pmp-NA4-X.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-R.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RW.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RWX.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-RX.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X-priority.S", + "rv32i_m/pmp32/src/pmp-NAPOT-X.S", + "rv32i_m/pmp32/src/pmp-TOR-R-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-R-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-R.S", + "rv32i_m/pmp32/src/pmp-TOR-RW-priority-level-2..S", + "rv32i_m/pmp32/src/pmp-TOR-RW-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-RW.S", + "rv32i_m/pmp32/src/pmp-TOR-RWX.S", + "rv32i_m/pmp32/src/pmp-TOR-RX-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-RX-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-RX.S", + "rv32i_m/pmp32/src/pmp-TOR-X-priority-level-2.S", + "rv32i_m/pmp32/src/pmp-TOR-X-priority.S", + "rv32i_m/pmp32/src/pmp-TOR-X.S" +}; + +string arch64pmp[] = '{ + `RISCVARCHTEST, + "rv64i_m/pmp64/pmp64-CFG-reg.S", + "rv64i_m/pmp64/pmp64-CSR-access.S", + "rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-R-priority.S", + "rv64i_m/pmp64/pmp64-NA4-R.S", + "rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-RW-priority.S", + "rv64i_m/pmp64/pmp64-NA4-RW.S", + "rv64i_m/pmp64/pmp64-NA4-RWX.S", + "rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-RX-priority.S", + "rv64i_m/pmp64/pmp64-NA4-RX.S", + "rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NA4-X-priority.S", + "rv64i_m/pmp64/pmp64-NA4-X.S", + "rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-R-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-R.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-RW.S", + "rv64i_m/pmp64/pmp64-NAPOT-RWX.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-RX.S", + "rv64i_m/pmp64/pmp64-NAPOT-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-NAPOT-X-priority.S", + "rv64i_m/pmp64/pmp64-NAPOT-X.S", + "rv64i_m/pmp64/pmp64-TOR-R-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-R-priority.S", + "rv64i_m/pmp64/pmp64-TOR-R.S", + "rv64i_m/pmp64/pmp64-TOR-RW-priority-level-2..S", + "rv64i_m/pmp64/pmp64-TOR-RW-priority.S", + "rv64i_m/pmp64/pmp64-TOR-RW.S", + "rv64i_m/pmp64/pmp64-TOR-RWX.S", + "rv64i_m/pmp64/pmp64-TOR-RX-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-RX-priority.S", + "rv64i_m/pmp64/pmp64-TOR-RX.S", + "rv64i_m/pmp64/pmp64-TOR-X-priority-level-2.S", + "rv64i_m/pmp64/pmp64-TOR-X-priority.S", + "rv64i_m/pmp64/pmp64-TOR-X.S" +}; + +string arch32vm_sv32[] = '{ + `RISCVARCHTEST, + "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S", + "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S", + "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S", + "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S", + "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S", + "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S", + "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S", + "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S", + "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S", + "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S", + "rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S" +}; + string arch64priv[] = '{ `RISCVARCHTEST, "rv64i_m/privilege/src/ebreak.S", diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 9abe67040..557d1af04 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -52,7 +52,7 @@ class sail_cSim(pluginTemplate): ispec = utils.load_yaml(isa_yaml)['hart0'] self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32') self.isa = 'rv' + self.xlen - self.sailargs = ' ' + self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 ')) if "I" in ispec["ISA"]: self.isa += 'i' @@ -103,7 +103,6 @@ class sail_cSim(pluginTemplate): execute = "@cd "+testentry['work_dir']+";" -# cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf cmd = self.compile_cmd.format(testentry['isa'].lower(), self.xlen) + ' ' + test + ' -o ' + elf compile_cmd = cmd + ' -D' + " -D".join(testentry['macros']) execute+=compile_cmd+";" @@ -117,8 +116,7 @@ class sail_cSim(pluginTemplate): reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test)) execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying else: - execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) -# execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) + execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) cov_str = ' ' for label in testentry['coverage_labels']: diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 3fde70700..0b07212cc 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -26,4 +26,4 @@ hart0: legal: - extensions[25:0] bitmask [0x000112D, 0x0000000] wr_illegal: - - Unchangedcd \ No newline at end of file + - Unchanged \ No newline at end of file