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				https://github.com/openhwgroup/cvw
				synced 2025-02-11 06:05:49 +00:00 
			
		
		
		
	Last of the branch predictor signal name updates.
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				@ -52,7 +52,7 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P)(
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  logic      RepairD;
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  logic      IncrRepairD, DecRepairD;
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  logic      DecrementPtr;
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  logic      DecPtr;
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  logic      FlushedReturnDE;
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  logic      WrongPredReturnD;
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@ -71,11 +71,11 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P)(
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  assign CounterEn = PopF | PushE | RepairD;
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  assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
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  assign DecPtr = (PopF | DecRepairD) & ~IncrRepairD;
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  assign P1 = 1;
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  assign M1 = '1; // -1
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  mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
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  mux2 #(Depth) PtrMux(P1, M1, DecPtr, IncDecPtr);
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  logic [Depth-1:0] Sum;
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  assign Sum = Ptr + IncDecPtr;
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  if(|P.RAS_SIZE[Depth-1:0])
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@ -47,7 +47,7 @@ module gshare import cvw::*; #(parameter cvw_t P,
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  logic                   MatchF, MatchD, MatchE, MatchM, MatchW;
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  logic                   MatchX;
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  logic [1:0]             PHTBPDirF, BPDirD, BPDirE, FwdNewDirPredF;
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  logic [1:0]             PHTBPDirF, BPDirD, BPDirE, FwdNewBPDirF;
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  logic [1:0]             NewBPDirE, NewBPDirM, NewBPDirW;
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  logic [k-1:0]           IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
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@ -78,12 +78,12 @@ module gshare import cvw::*; #(parameter cvw_t P,
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  assign MatchW = BranchW & ~FlushW & (IndexF == IndexW);
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  assign MatchX = MatchD | MatchE | MatchM | MatchW;
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  assign FwdNewDirPredF = MatchD ? {2{BPDirD[1]}} :
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  assign FwdNewBPDirF = MatchD ? {2{BPDirD[1]}} :
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                                   MatchE ? {NewBPDirE} :
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                                   MatchM ? {NewBPDirM} :
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                   NewBPDirW ;
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  assign BPDirF = MatchX ? FwdNewDirPredF : PHTBPDirF;
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  assign BPDirF = MatchX ? FwdNewBPDirF : PHTBPDirF;
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  ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
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    .ce1(~StallF), .ce2(~StallW & ~FlushW),
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