From 0ca10e7ee2e3e2feaec797e8b0defcc18f14f9cf Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Sun, 2 Jun 2024 17:01:51 -0500
Subject: [PATCH] Last of the branch predictor signal name updates.

---
 src/ifu/bpred/RASPredictor.sv | 6 +++---
 src/ifu/bpred/gshare.sv       | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
index 5129e9043..f045533e3 100644
--- a/src/ifu/bpred/RASPredictor.sv
+++ b/src/ifu/bpred/RASPredictor.sv
@@ -52,7 +52,7 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P)(
   logic      RepairD;
   logic      IncrRepairD, DecRepairD;
   
-  logic      DecrementPtr;
+  logic      DecPtr;
   logic      FlushedReturnDE;
   logic      WrongPredReturnD;
   
@@ -71,11 +71,11 @@ module RASPredictor import cvw::*;  #(parameter cvw_t P)(
     
   assign CounterEn = PopF | PushE | RepairD;
 
-  assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
+  assign DecPtr = (PopF | DecRepairD) & ~IncrRepairD;
 
   assign P1 = 1;
   assign M1 = '1; // -1
-  mux2 #(Depth) PtrMux(P1, M1, DecrementPtr, IncDecPtr);
+  mux2 #(Depth) PtrMux(P1, M1, DecPtr, IncDecPtr);
   logic [Depth-1:0] Sum;
   assign Sum = Ptr + IncDecPtr;
   if(|P.RAS_SIZE[Depth-1:0])
diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
index 149b2f353..f17156c25 100644
--- a/src/ifu/bpred/gshare.sv
+++ b/src/ifu/bpred/gshare.sv
@@ -47,7 +47,7 @@ module gshare import cvw::*; #(parameter cvw_t P,
   logic                   MatchF, MatchD, MatchE, MatchM, MatchW;
   logic                   MatchX;
 
-  logic [1:0]             PHTBPDirF, BPDirD, BPDirE, FwdNewDirPredF;
+  logic [1:0]             PHTBPDirF, BPDirD, BPDirE, FwdNewBPDirF;
   logic [1:0]             NewBPDirE, NewBPDirM, NewBPDirW;
 
   logic [k-1:0]           IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
@@ -78,12 +78,12 @@ module gshare import cvw::*; #(parameter cvw_t P,
   assign MatchW = BranchW & ~FlushW & (IndexF == IndexW);
   assign MatchX = MatchD | MatchE | MatchM | MatchW;
 
-  assign FwdNewDirPredF = MatchD ? {2{BPDirD[1]}} :
+  assign FwdNewBPDirF = MatchD ? {2{BPDirD[1]}} :
                                    MatchE ? {NewBPDirE} :
                                    MatchM ? {NewBPDirM} :
                    NewBPDirW ;
   
-  assign BPDirF = MatchX ? FwdNewDirPredF : PHTBPDirF;
+  assign BPDirF = MatchX ? FwdNewBPDirF : PHTBPDirF;
 
   ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallW & ~FlushW),