diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv
index a63bf9824..c31dca1d7 100644
--- a/pipelined/src/privileged/privdec.sv
+++ b/pipelined/src/privileged/privdec.sv
@@ -52,7 +52,7 @@ module privdec (
   // Decode privileged instructions
   ///////////////////////////////////////////
   assign sretM =      PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & 
-                      (PrivilegeModeW == `M_MODE || PrivilegeModeW == `S_MODE & ~STATUS_TSR); 
+                      (PrivilegeModeW == `M_MODE | PrivilegeModeW == `S_MODE & ~STATUS_TSR); 
   assign mretM =      PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE);
   assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000);
   assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001);
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index c5c749b8d..ec3cc8634 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -68,7 +68,7 @@ module trap (
   assign Committed = CommittedM | CommittedF;
   assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
   assign ValidIntsM = {12{~Committed}} & EnabledIntsM;
-  assign InterruptM = (|ValidIntsM) && InstrValidM; // suppress interrupt if the memory system has partially processed a request.
+  assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
   assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & 
                      (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);