Merge pull request #97 from davidharrishmc/dev

Synthesis improvements

config/buildroot/wally-config.vh

@@ -132,6 +132,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 
 `define HPTW_WRITES_SUPPORTED 1

config/fpga/wally-config.vh

@@ -141,6 +141,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 
 `define HPTW_WRITES_SUPPORTED 1

config/rv32e/wally-config.vh

@@ -136,6 +136,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 

config/rv32gc/wally-config.vh

@@ -135,6 +135,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 

config/rv32i/wally-config.vh

@@ -136,6 +136,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 

config/rv32imc/wally-config.vh

@@ -68,7 +68,7 @@
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
-`define IDIV_BITSPERCYCLE 4
+`define IDIV_BITSPERCYCLE 2
 `define IDIV_ON_FPU 0
 
 // Legal number of PMP entries are 0, 16, or 64
@@ -135,6 +135,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 

config/rv64fpquad/wally-config.vh

@@ -138,6 +138,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 

config/rv64gc/wally-config.vh

@@ -138,6 +138,7 @@
 `define BPRED_SUPPORTED 1
 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 

config/rv64i/wally-config.vh

@@ -138,6 +138,7 @@
 `define BPRED_SUPPORTED 0
 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
+`define BTB_SIZE (`BPRED_SIZE)
 
 `define HPTW_WRITES_SUPPORTED 0
 

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -129,7 +129,6 @@ module fdivsqrtpreproc (
 
     // pipeline registers
     flopen #(1)        mdureg(clk, IFDivStartE, IntDivE,     IntDivM);
-    flopen #(1)        w64reg(clk, IFDivStartE, W64E,     W64M);
     flopen #(1)       altbreg(clk, IFDivStartE, ALTBE,    ALTBM);
     flopen #(1)    negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
     flopen #(1)      bzeroreg(clk, IFDivStartE, BZeroE,   BZeroM);
@@ -137,6 +136,8 @@ module fdivsqrtpreproc (
     flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE,       nM);
     flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE,       mM);
     flopen #(`XLEN)   srcareg(clk, IFDivStartE, AE,       AM);
+    if (`XLEN==64) 
+      flopen #(1)      w64reg(clk, IFDivStartE, W64E,     W64M);
 
   end else begin // Int not supported
     assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};

src/ifu/bpred/bpred.sv

@@ -137,7 +137,8 @@ module bpred (
   // Part 2 Branch target address prediction
   // BTB contains target address for all CFI
 
-  btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
+  btb #(`BTB_SIZE) 
+    TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
           .PCNextF, .PCF, .PCD, .PCE,
           .PredPCF,
           .BTBPredInstrClassF,

src/lsu/dtim.sv

@@ -42,12 +42,16 @@ module dtim(
 
   logic                      we;
  
-  localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8);
-  localparam OFFSET     = $clog2(`LLEN/8);
+  localparam LLENBYTES  = `LLEN/8;
+  // verilator  lint_off WIDTH 
+  localparam DEPTH      = `DTIM_RANGE/LLENBYTES;
+  // verilator  lint_on WIDTH 
+  localparam ADDR_WDITH = $clog2(DEPTH);
+  localparam OFFSET     = $clog2(LLENBYTES);
 
   assign we = MemRWM[0]  & ~FlushW;  // have to ignore write if Trap.
 
-  ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) 
+  ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(`LLEN)) 
     ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
   

src/mmu/mmu.sv

@@ -107,15 +107,21 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
     .Cacheable, .Idempotent, .SelTIM,
     .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
  
-  pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
-    .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
-    .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
-    .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
+  if (`PMP_ENTRIES > 0) 
+    pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW,
+      .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
+      .ExecuteAccessF, .WriteAccessM, .ReadAccessM,
+      .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
+  else begin
+    assign PMPInstrAccessFaultF     = 0;
+    assign PMPStoreAmoAccessFaultM  = 0;
+    assign PMPLoadAccessFaultM      = 0;
+  end
 
   // Access faults
   // If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
-  assign InstrAccessFaultF    = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit);
-  assign LoadAccessFaultM     = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit);
+  assign InstrAccessFaultF    = (PMAInstrAccessFaultF    | PMPInstrAccessFaultF)    & ~(Translate & ~TLBHit);
+  assign LoadAccessFaultM     = (PMALoadAccessFaultM     | PMPLoadAccessFaultM)     & ~(Translate & ~TLBHit);
   assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit);
 
   // Misaligned faults

src/mmu/pmpchecker.sv

@@ -49,15 +49,15 @@ module pmpchecker (
   output logic                     PMPStoreAmoAccessFaultM
 );
 
-  if (`PMP_ENTRIES > 0) begin
-    // Bit i is high when the address falls in PMP region i
-    logic                    EnforcePMP;
-    logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
-    logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
-    logic [`PMP_ENTRIES-1:0] Active;     // PMP register i is non-null
-    logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
-    logic [`PMP_ENTRIES-1:0]   PAgePMPAdr;  // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
+  // Bit i is high when the address falls in PMP region i
+  logic                    EnforcePMP;
+  logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
+  logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
+  logic [`PMP_ENTRIES-1:0] Active;     // PMP register i is non-null
+  logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
+  logic [`PMP_ENTRIES-1:0]   PAgePMPAdr;  // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
 
+  if (`PMP_ENTRIES > 0) 
     pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
       .PhysicalAddress, 
       .PMPCfg(PMPCFG_ARRAY_REGW),
@@ -66,17 +66,12 @@ module pmpchecker (
       .PAgePMPAdrOut(PAgePMPAdr),
       .Match, .Active, .L, .X, .W, .R);
 
-    priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
+  priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
 
-    // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
-    assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; 
+  // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region
+  assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; 
 
-    assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
-    assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
-    assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
-  end else begin
-    assign PMPInstrAccessFaultF     = 0;
-    assign PMPStoreAmoAccessFaultM  = 0;
-    assign PMPLoadAccessFaultM      = 0;
-  end
+  assign PMPInstrAccessFaultF     = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
+  assign PMPStoreAmoAccessFaultM  = EnforcePMP & WriteAccessM   & ~|(W & FirstMatch) ;
+  assign PMPLoadAccessFaultM      = EnforcePMP & ReadAccessM    & ~|(R & FirstMatch) ;
  endmodule

synthDC/Makefile

@@ -89,6 +89,7 @@ endif
 # when mod = noPriv, the privileged unit and PMP are disabled
 # when mod = noFPU, the FPU, privileged unit, and PMP are disabled
 # when mod = noMulDiv, the MDU, FPU, privileged unit, and PMP are disabled.
+# when mod = noAtomic, the Atomic, MDU, FPU, privileged unit, and PMP are disabled
 
 ifneq ($(MOD), orig)
 	# PMP 0
@@ -103,6 +104,10 @@ ifneq ($(MOD), noPriv)
 ifneq ($(MOD), noFPU)
 	# no muldiv
 	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh
+ifneq ($(MOD), noMulDiv)
+	# no atomic
+	sed -i 's/1 *<< *0/0 << 0/' $(CONFIGDIR)/wally-config.vh
+endif
 endif
 endif
 endif

synthDC/extractArea.pl

@@ -0,0 +1,118 @@
+#!/bin/perl -W
+
+###########################################
+## extractArea.pl
+##
+## Written: David_Harris@hmc.edu 
+## Created: 19 Feb 2023
+## Modified: 
+##
+## Purpose: Pull area statistics from run directory
+##
+## A component of the CORE-V-WALLY configurable RISC-V project.
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+
+
+use strict;
+use warnings;
+import os;
+
+my %configResults;
+my $dir = "runs";
+my $macro = "Macro/Black Box area:";
+my $seq = "Noncombinational area:";
+my $buf = "Buf/Inv area:";
+my $comb = "Combinational area:";
+my $macroC = "Number of macros/black boxes:";
+my $seqC = "Number of sequential cells:";
+my $bufC = "Number of buf/inv:";
+my $combC = "Number of combinational cells:";
+my @keywords = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", $macro, $seq, $buf, $comb, $macroC, $seqC, $bufC, $combC);
+my @keywordsp = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", 
+                 "RAMs", "Flip-flops", "Inv/Buf", "Logic", "RAMs Cnt", "Flip-flops Cnt", "Inv/Buf Cnt", "Logic Cnt", "Total Cnt");
+my @configs = ("rv32e", "rv32i", "rv32imc", "rv32gc", "rv64i", "rv64gc");
+
+opendir(DIR, $dir) or die "Could not open $dir";
+
+while (my $filename = readdir(DIR)) {
+    if ($filename =~ /orig_tsmc28psyn/) {
+#        print "$filename\n";
+        &processRun("$dir/$filename");
+    }
+}
+closedir(DIR);
+
+# print table of results
+printf("%20s\t", "");
+foreach my $config (@configs) {
+    printf("%s\t", $config);
+}
+print ("\n");
+foreach my $kw (@keywordsp) {
+    my $kws = substr($kw, 0, 3);
+    printf("%20s\t", $kw);
+    foreach my $config (@configs) {
+        my $r = $configResults{$config};
+        if (exists ${$r}{$kw}) {
+            my $area = ${$r}{$kw};
+            while ($area =~ s/(\d+)(\d\d\d)/$1\,$2/){};
+            #print "${$r}{$kw}\t";
+            print "$area\t";
+        } else {
+            print("\t");
+        }        
+    }
+    print("\n");
+}
+
+sub processRun {
+    my $fname = shift;
+    my $ffname = "$fname/reports/wallypipelinedcore_area.rep";
+    open(FILE, "$ffname") or die ("Could not read $ffname");
+
+    # Extract configuration from fname;
+    $fname =~ /_([^_]*)_orig/; 
+    my $config = $1;
+    #print("Reading $config from $ffname\n");
+
+    # Search for results
+    my %results;
+    while (my $line = <FILE>) {
+        foreach my $kw (@keywords) {
+           # print "$kw $line\n";
+            if ($line =~ /^${kw}\s+(\S*)/) {
+                #print "$line $kw $1\n";
+                $results{$kw} = int($1);
+            }
+        }
+    }
+    foreach my $kw (@keywords) {
+        #print "$kw\t$results{$kw}\n";
+    }
+    $results{"Logic"} = $results{$comb} - $results{$buf};
+    $results{"Inv/Buf"} = $results{$buf};
+    $results{"Flip-flops"} = $results{$seq};
+    $results{"RAMs"} = $results{$macro};
+    $results{"Logic Cnt"} = $results{$combC} - $results{$bufC};
+    $results{"Inv/Buf Cnt"} = $results{$bufC};
+    $results{"Flip-flops Cnt"} = $results{$seqC};
+    $results{"RAMs Cnt"} = $results{$macroC};
+    $results{"Total Cnt"} = $results{$macroC} + $results{$seqC} +  $results{$combC};
+    close(FILE);
+    $configResults{$config} = \%results;
+}

synthDC/extractSummary.py

@@ -263,3 +263,4 @@ if __name__ == '__main__':
     plotConfigs('sky90', mod='orig')
     plotConfigs('tsmc28psyn', mod='orig')
     normAreaDelay(mod='orig')
+    os.system("./extractArea.pl");

synthDC/wallySynth.py

@@ -56,7 +56,7 @@ if __name__ == '__main__':
         defaultfreq = 500 if tech == 'sky90' else 1500
         freq = args.targetfreq if args.targetfreq else defaultfreq
         config = args.version if args.version else 'rv64gc'
-        for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: 
+        for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'PMP0']: 
             runSynth(config, mod, tech, freq, maxopt, usesram)
     else:
         defaultfreq = 500 if tech == 'sky90' else 1500