From 8db49c83c4ade951404698a85b7b05f45bdb5a9d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 07:03:31 -0800 Subject: [PATCH 01/11] Disabled W64M register for RV32 --- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 5d490df28..0a96e1b1a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -129,7 +129,6 @@ module fdivsqrtpreproc ( // pipeline registers flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM); - flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M); flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM); flopen #(1) negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM); flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM); @@ -137,6 +136,8 @@ module fdivsqrtpreproc ( flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, nE, nM); flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM); flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM); + if (`XLEN==64) + flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M); end else begin // Int not supported assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}}; From ec3ab7a93b61a892e5e154a36d10a54b8327909d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 15:29:41 -0800 Subject: [PATCH 02/11] New extractArea script to generate area tables --- synthDC/extractArea.pl | 118 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100755 synthDC/extractArea.pl diff --git a/synthDC/extractArea.pl b/synthDC/extractArea.pl new file mode 100755 index 000000000..d16c74df5 --- /dev/null +++ b/synthDC/extractArea.pl @@ -0,0 +1,118 @@ +#!/bin/perl -W + +########################################### +## extractArea.pl +## +## Written: David_Harris@hmc.edu +## Created: 19 Feb 2023 +## Modified: +## +## Purpose: Pull area statistics from run directory +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org/licenses/SHL-2.1/ +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ + + +use strict; +use warnings; +import os; + +my %configResults; +my $dir = "runs"; +my $macro = "Macro/Black Box area:"; +my $seq = "Noncombinational area:"; +my $buf = "Buf/Inv area:"; +my $comb = "Combinational area:"; +my $macroC = "Number of macros/black boxes:"; +my $seqC = "Number of sequential cells:"; +my $bufC = "Number of buf/inv:"; +my $combC = "Number of combinational cells:"; +my @keywords = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", $macro, $seq, $buf, $comb, $macroC, $seqC, $bufC, $combC); +my @keywordsp = ("ifu", "ieu", "lsu", "hzu", "ebu.ebu", "priv.priv", "mdu.mdu", "fpu.fpu", "wallypipelinedcore", + "RAMs", "Flip-flops", "Inv/Buf", "Logic", "RAMs Cnt", "Flip-flops Cnt", "Inv/Buf Cnt", "Logic Cnt", "Total Cnt"); +my @configs = ("rv32e", "rv32i", "rv32imc", "rv32gc", "rv64i", "rv64gc"); + +opendir(DIR, $dir) or die "Could not open $dir"; + +while (my $filename = readdir(DIR)) { + if ($filename =~ /orig_tsmc28psyn/) { +# print "$filename\n"; + &processRun("$dir/$filename"); + } +} +closedir(DIR); + +# print table of results +printf("%20s\t", ""); +foreach my $config (@configs) { + printf("%s\t", $config); +} +print ("\n"); +foreach my $kw (@keywordsp) { + my $kws = substr($kw, 0, 3); + printf("%20s\t", $kw); + foreach my $config (@configs) { + my $r = $configResults{$config}; + if (exists ${$r}{$kw}) { + my $area = ${$r}{$kw}; + while ($area =~ s/(\d+)(\d\d\d)/$1\,$2/){}; + #print "${$r}{$kw}\t"; + print "$area\t"; + } else { + print("\t"); + } + } + print("\n"); +} + +sub processRun { + my $fname = shift; + my $ffname = "$fname/reports/wallypipelinedcore_area.rep"; + open(FILE, "$ffname") or die ("Could not read $ffname"); + + # Extract configuration from fname; + $fname =~ /_([^_]*)_orig/; + my $config = $1; + #print("Reading $config from $ffname\n"); + + # Search for results + my %results; + while (my $line = ) { + foreach my $kw (@keywords) { + # print "$kw $line\n"; + if ($line =~ /^${kw}\s+(\S*)/) { + #print "$line $kw $1\n"; + $results{$kw} = int($1); + } + } + } + foreach my $kw (@keywords) { + #print "$kw\t$results{$kw}\n"; + } + $results{"Logic"} = $results{$comb} - $results{$buf}; + $results{"Inv/Buf"} = $results{$buf}; + $results{"Flip-flops"} = $results{$seq}; + $results{"RAMs"} = $results{$macro}; + $results{"Logic Cnt"} = $results{$combC} - $results{$bufC}; + $results{"Inv/Buf Cnt"} = $results{$bufC}; + $results{"Flip-flops Cnt"} = $results{$seqC}; + $results{"RAMs Cnt"} = $results{$macroC}; + $results{"Total Cnt"} = $results{$macroC} + $results{$seqC} + $results{$combC}; + close(FILE); + $configResults{$config} = \%results; +} \ No newline at end of file From fa0406b554aeaae8427a08854cc3a32fc16c0d64 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 15:31:00 -0800 Subject: [PATCH 03/11] Moved conditional instantiation outside pmpchecker --- src/mmu/mmu.sv | 18 +++++++++++------ src/mmu/pmpchecker.sv | 46 +++++++++++++++++++------------------------ 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index 8a440c39d..5b5248161 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -107,15 +107,21 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( .Cacheable, .Idempotent, .SelTIM, .PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM); - pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW, - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, - .ExecuteAccessF, .WriteAccessM, .ReadAccessM, - .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM); + if (`PMP_ENTRIES > 0) + pmpchecker pmpchecker(.PhysicalAddress, .PrivilegeModeW, + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, + .ExecuteAccessF, .WriteAccessM, .ReadAccessM, + .PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM); + else begin + assign PMPInstrAccessFaultF = 0; + assign PMPStoreAmoAccessFaultM = 0; + assign PMPLoadAccessFaultM = 0; + end // Access faults // If TLB miss and translating we want to not have faults from the PMA and PMP checkers. - assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit); - assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit); + assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~(Translate & ~TLBHit); + assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~(Translate & ~TLBHit); assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM) & ~(Translate & ~TLBHit); // Misaligned faults diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index a57961365..de8ce7b31 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -49,34 +49,28 @@ module pmpchecker ( output logic PMPStoreAmoAccessFaultM ); - if (`PMP_ENTRIES > 0) begin - // Bit i is high when the address falls in PMP region i - logic EnforcePMP; - logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges - logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address. - logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null - logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set - logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] + // Bit i is high when the address falls in PMP region i + logic EnforcePMP; + logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges + logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address. + logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null + logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set + logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] - pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0]( - .PhysicalAddress, - .PMPCfg(PMPCFG_ARRAY_REGW), - .PMPAdr(PMPADDR_ARRAY_REGW), - .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), - .PAgePMPAdrOut(PAgePMPAdr), - .Match, .Active, .L, .X, .W, .R); + pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0]( + .PhysicalAddress, + .PMPCfg(PMPCFG_ARRAY_REGW), + .PMPAdr(PMPADDR_ARRAY_REGW), + .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), + .PAgePMPAdrOut(PAgePMPAdr), + .Match, .Active, .L, .X, .W, .R); - priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. + priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. - // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; + // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region + assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; - assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; - assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ; - assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ; - end else begin - assign PMPInstrAccessFaultF = 0; - assign PMPStoreAmoAccessFaultM = 0; - assign PMPLoadAccessFaultM = 0; - end + assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; + assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ; + assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ; endmodule From 5ce50103f9b0d7282b3f5f3cf6b45099e197001d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 15:31:33 -0800 Subject: [PATCH 04/11] Run extractArea at end of extractSummary --- synthDC/extractSummary.py | 1 + 1 file changed, 1 insertion(+) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 85bc6f0aa..94902f9c9 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -263,3 +263,4 @@ if __name__ == '__main__': plotConfigs('sky90', mod='orig') plotConfigs('tsmc28psyn', mod='orig') normAreaDelay(mod='orig') + os.system("./extractArea.pl"); From bbdad235ef3eb56fb298b467f2c535c6a2db102a Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 15:32:32 -0800 Subject: [PATCH 05/11] Removed orig feature from featuresweep to avoid redundancy with configsweep --- synthDC/wallySynth.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 73bb58698..831ffca2e 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -56,7 +56,7 @@ if __name__ == '__main__': defaultfreq = 500 if tech == 'sky90' else 1500 freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' - for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: + for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0']: runSynth(config, mod, tech, freq, maxopt, usesram) else: defaultfreq = 500 if tech == 'sky90' else 1500 From 00d54cfe6cb85099c9498277647d8ad2fd24d4ed Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 16:08:23 -0800 Subject: [PATCH 06/11] PMP checker size check to avoid spurious warnings --- src/mmu/pmpchecker.sv | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index de8ce7b31..9c9c745bb 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -57,13 +57,14 @@ module pmpchecker ( logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] - pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0]( - .PhysicalAddress, - .PMPCfg(PMPCFG_ARRAY_REGW), - .PMPAdr(PMPADDR_ARRAY_REGW), - .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), - .PAgePMPAdrOut(PAgePMPAdr), - .Match, .Active, .L, .X, .W, .R); + if (`PMP_ENTRIES > 0) + pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0]( + .PhysicalAddress, + .PMPCfg(PMPCFG_ARRAY_REGW), + .PMPAdr(PMPADDR_ARRAY_REGW), + .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), + .PAgePMPAdrOut(PAgePMPAdr), + .Match, .Active, .L, .X, .W, .R); priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. From 5287c54278f4ece65c9ecb96164844ae63854f12 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 16:14:38 -0800 Subject: [PATCH 07/11] Adjusted DTIM to always be 512B independent of XLEN --- src/lsu/dtim.sv | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 4a5cba1f2..9383b7760 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -42,12 +42,16 @@ module dtim( logic we; - localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8); - localparam OFFSET = $clog2(`LLEN/8); + localparam LLENBYTES = `LLEN/8; + // verilator lint_off WIDTH + localparam DEPTH = `DTIM_RANGE/LLENBYTES; + // verilator lint_on WIDTH + localparam ADDR_WDITH = $clog2(DEPTH); + localparam OFFSET = $clog2(LLENBYTES); assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. - ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) + ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(`LLEN)) ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); endmodule From 20ced0653cd8c08cd9994a537bb55a89008bc5d2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 19:59:07 -0800 Subject: [PATCH 08/11] Parameterized btb to depend on BPRED_SIZE --- src/ifu/bpred/bpred.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index a65633c92..aacf3b69f 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -137,7 +137,8 @@ module bpred ( // Part 2 Branch target address prediction // BTB contains target address for all CFI - btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, + btb #(`BPRED_SIZE) + TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, .PCNextF, .PCF, .PCD, .PCE, .PredPCF, .BTBPredInstrClassF, From 816e8ab1cb1f8e71ae8dca6c754522a3edf2dc4b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 19:59:30 -0800 Subject: [PATCH 09/11] Reduced rv32imc int divider to 2 copies to avoid it being on the critical path --- config/rv32imc/wally-config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh index 010b6599f..52dfef069 100644 --- a/config/rv32imc/wally-config.vh +++ b/config/rv32imc/wally-config.vh @@ -68,7 +68,7 @@ // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 +`define IDIV_BITSPERCYCLE 2 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 From 3f24238d02912d88a97a21c538e9edc9efb8b455 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 20:05:39 -0800 Subject: [PATCH 10/11] Added noAtomic feature to swweep --- synthDC/Makefile | 5 +++++ synthDC/wallySynth.py | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 034b2f86e..5ea9677c5 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -89,6 +89,7 @@ endif # when mod = noPriv, the privileged unit and PMP are disabled # when mod = noFPU, the FPU, privileged unit, and PMP are disabled # when mod = noMulDiv, the MDU, FPU, privileged unit, and PMP are disabled. +# when mod = noAtomic, the Atomic, MDU, FPU, privileged unit, and PMP are disabled ifneq ($(MOD), orig) # PMP 0 @@ -103,6 +104,10 @@ ifneq ($(MOD), noPriv) ifneq ($(MOD), noFPU) # no muldiv sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/wally-config.vh +ifneq ($(MOD), noMulDiv) + # no atomic + sed -i 's/1 *<< *0/0 << 0/' $(CONFIGDIR)/wally-config.vh +endif endif endif endif diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 831ffca2e..139bcdd60 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -56,7 +56,7 @@ if __name__ == '__main__': defaultfreq = 500 if tech == 'sky90' else 1500 freq = args.targetfreq if args.targetfreq else defaultfreq config = args.version if args.version else 'rv64gc' - for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0']: + for mod in ['noAtomic', 'noFPU', 'noMulDiv', 'noPriv', 'PMP0']: runSynth(config, mod, tech, freq, maxopt, usesram) else: defaultfreq = 500 if tech == 'sky90' else 1500 From d07c6386b2b15cd02e26329ea4d37bfbf004c51f Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 19 Feb 2023 20:13:50 -0800 Subject: [PATCH 11/11] Added BTB_SIZE parameter independent of BPRED_SIIZE --- config/buildroot/wally-config.vh | 1 + config/fpga/wally-config.vh | 1 + config/rv32e/wally-config.vh | 1 + config/rv32gc/wally-config.vh | 1 + config/rv32i/wally-config.vh | 1 + config/rv32imc/wally-config.vh | 1 + config/rv64fpquad/wally-config.vh | 1 + config/rv64gc/wally-config.vh | 1 + config/rv64i/wally-config.vh | 1 + src/ifu/bpred/bpred.sv | 2 +- 10 files changed, 10 insertions(+), 1 deletion(-) diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh index f10e11f99..656bfbe4c 100644 --- a/config/buildroot/wally-config.vh +++ b/config/buildroot/wally-config.vh @@ -132,6 +132,7 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 1 diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index d0299c4e3..a4c97a86e 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -141,6 +141,7 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 1 diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh index 8cd9ca3f4..8a0dd5f4b 100644 --- a/config/rv32e/wally-config.vh +++ b/config/rv32e/wally-config.vh @@ -136,6 +136,7 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 0 diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh index e45c2b093..07b4668ec 100644 --- a/config/rv32gc/wally-config.vh +++ b/config/rv32gc/wally-config.vh @@ -135,6 +135,7 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 0 diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index d400cebe9..4ef0b60e7 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -136,6 +136,7 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 0 diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh index 52dfef069..19da7c42f 100644 --- a/config/rv32imc/wally-config.vh +++ b/config/rv32imc/wally-config.vh @@ -135,6 +135,7 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 0 diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh index 23a9aa05e..7f0c2a048 100644 --- a/config/rv64fpquad/wally-config.vh +++ b/config/rv64fpquad/wally-config.vh @@ -138,6 +138,7 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 0 diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh index 0b8a932d6..d163dc34b 100644 --- a/config/rv64gc/wally-config.vh +++ b/config/rv64gc/wally-config.vh @@ -138,6 +138,7 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 0 diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh index 627cac8f7..24a171a75 100644 --- a/config/rv64i/wally-config.vh +++ b/config/rv64i/wally-config.vh @@ -138,6 +138,7 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPRED_SIZE 10 +`define BTB_SIZE (`BPRED_SIZE) `define HPTW_WRITES_SUPPORTED 0 diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index aacf3b69f..1903ed984 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -137,7 +137,7 @@ module bpred ( // Part 2 Branch target address prediction // BTB contains target address for all CFI - btb #(`BPRED_SIZE) + btb #(`BTB_SIZE) TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, .PCNextF, .PCF, .PCD, .PCE, .PredPCF,