mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw
This commit is contained in:
Rose Thompson
commit
0a660c64fc
@ -11,11 +11,13 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
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$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
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$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
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ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
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ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbc_zbs
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#ARCH := rv$(XLEN)gc_zba_zbb_zbc_zbs
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#ARCH := rv$(XLEN)gc
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ARCH := rv$(XLEN)imc_zicsr
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#ARCH := rv$(XLEN)imc_zicsr
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#ARCH := rv$(XLEN)im_zicsr
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#ARCH := rv$(XLEN)i_zicsr
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PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
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-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
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-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
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@ -23,6 +25,24 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
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-nostdlib -nostartfiles -ffreestanding -mstrict-align \
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-DTOTAL_DATA_SIZE=2000 -DMAIN_HAS_NOARGC=1 -DPERFORMANCE_RUN=1 -DITERATIONS=10 -DXLEN=$(XLEN)
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# Black Parrott
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#PORT_CFLAGS = -O2 -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4 \
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-DITERATIONS=10 -DPERFORMANCE_RUN=1
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#OPTIMIZE := -O2 -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4
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#override CFLAGS += $(OPTIMIZE) -DFLAGS_STR=\""$(OPTIMIZE)"\"
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#override CFLAGS += -DITERATIONS=10 -DPERFORMANCE_RUN=1
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# try adding the new fields from muntjac coremark build
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#PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
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-fno-common -flto -funswitch-loops -mcmodel=medany \
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-falign-functions=4 -falign-jumps=4 -falign-loops=4 \
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-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions --param max-inline-insns-auto=20 -falign-jumps=4 \
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-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
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-funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta \
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-nostdlib -nostartfiles -ffreestanding -mstrict-align \
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-DTOTAL_DATA_SIZE=2000 -DMAIN_HAS_NOARGC=1 -DPERFORMANCE_RUN=1 -DITERATIONS=10 -DXLEN=$(XLEN)
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all: $(work_dir)/coremark.bare.riscv.elf.memfile
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run:
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43
sim/verilate
43
sim/verilate
@ -1,21 +1,42 @@
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#!/bin/bash
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# simulate with Verilator
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# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
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# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
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export PATH=$PATH:/usr/local/bin/
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verilator=`which verilator`
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basepath=$(dirname $0)/..
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#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
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for config in rv64gc; do
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echo "$config simulating..."
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# not working: -GTEST="arch64i"
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if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"arch64i\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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echo "Exiting after $config lint due to errors or warnings"
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exit 1
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fi
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./obj_dir/Vtestbench
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# define associateive array of tests to run
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declare -A suites
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rv64gccases=("arch64zba" "arch64zbb" "arch64zbc" "arch64zbs" "arch64i" "arch64m" "arch64a" "arch64f" "arch64d" "arch64c" "arch64f_fma" "arch64d_fma" "wally64priv")
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suites["rv64gc"]=${rv64gccases[@]}
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rv64icases=("arch64i")
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suites["rv64i"]=${rv32icases[@]}
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rv32gccases=("arch32zba" "arch32zbb" "arch32zbc" "arch32zbs" "arch32i" "arch32m" "arch32a" "arch32f" "arch32d" "arch32c" "arch64f_fma" "arch64d_fma" "wally32priv")
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suites["rv32gc"]=${rv32gccases[@]}
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rv32imccases=("arch32i" "arch32m" "arch32c")
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suites["rv32imc"]=${rv32imccases[@]}
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rv32icases=("arch32i")
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suites["rv32i"]=${rv32icases[@]}
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rv32ecases=("arch32e")
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suites["rv32e"]=${rv32ecases[@]}
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for config in ${!suites[@]}; do
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for suite in ${suites[${config}]}; do
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echo "Verilating ${config} ${suite}"
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if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"${suite}\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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echo "Exiting after ${config} ${suite} verilation due to errors or warnings"
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exit 1
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fi
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./obj_dir/Vtestbench
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done
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done
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echo "Verilation complete"
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# command line to invoke Verilator on rv64gc arch64i
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# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
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# command line with debugging to address core dumps
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# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
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@ -388,11 +388,10 @@ module testbench;
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end
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end
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// *** 06 January 2024 RT: may have to uncomment this block for vcs/verilator
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integer adrindex;
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if (P.UNCORE_RAM_SUPPORTED)
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always @(posedge clk)
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if (ResetMem) // program memory is sometimes reset
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if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
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for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
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dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
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@ -442,6 +441,15 @@ module testbench;
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clk = 1; # 5; clk = 0; # 5;
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end
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/*
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// Print key info each cycle for debugging
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always @(posedge clk) begin
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#2;
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$display("PCM: %x InstrM: %x (%5s) WriteDataM: %x IEUResultM: %x",
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dut.core.PCM, dut.core.InstrM, InstrMName, dut.core.WriteDataM, dut.core.ieu.dp.IEUResultM);
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end
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*/
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////////////////////////////////////////////////////////////////////////////////
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// Support logic
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////////////////////////////////////////////////////////////////////////////////
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@ -504,49 +512,66 @@ module testbench;
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input logic riscofTest;
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input integer begin_signature_addr;
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output integer errors;
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int fd, code;
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string line;
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int siglines, sigentries;
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localparam SIGNATURESIZE = 5000000;
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integer i;
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logic [31:0] sig32[0:SIGNATURESIZE];
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logic [31:0] parsed;
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logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
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string signame;
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logic [P.XLEN-1:0] testadr, testadrNoBase;
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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sig32[i] = 'bx;
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end
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// read .signature.output file and compare to check for errors
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if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
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else signame = {pathname, TestName, ".signature.output"};
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// read signature, reformat in 64 bits if necessary
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$readmemh(signame, sig32);
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i = 0;
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while (i < SIGNATURESIZE) begin
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if (P.XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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end
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if (i >= 4 & sig32[i-4] === 'bx) begin
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if (i == 4) begin
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i = SIGNATURESIZE+1; // flag empty file
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$display(" Error: empty test file");
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end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
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// read signature file from memory and count lines. Can't use readmemh because we need the line count
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// $readmemh(signame, sig32);
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fd = $fopen(signame, "r");
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siglines = 0;
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if (fd == 0) $display("Unable to read %s", signame);
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else begin
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while (!$feof(fd)) begin
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code = $fgets(line, fd);
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if (code != 0) begin
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int errno;
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string errstr;
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errno = $ferror(fd, errstr);
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if (errno != 0) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr);
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if (line.len() > 1) begin // skip blank lines
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if ($sscanf(line, "%x", parsed) != 0) begin
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sig32[siglines] = parsed;
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siglines = siglines + 1; // increment if line is not blank
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end
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end
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end
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end
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$fclose(fd);
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end
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// Check valid number of lines were read
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if (siglines == 0) begin
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errors = 1;
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$display("Error: empty test file %s", signame);
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end else if (P.XLEN == 64 & (siglines % 2)) begin
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errors = 1;
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$display("Error: RV64 signature has odd number of lines %s", signame);
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end else errors = 0;
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// copy lines into signature, converting to XLEN if necessary
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sigentries = (P.XLEN == 32) ? siglines : siglines/2; // number of signature entries
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for (i=0; i<sigentries; i++) begin
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signature[i] = (P.XLEN == 32) ? sig32[i] : {sig32[i*2+1], sig32[i*2]};
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//$display("XLEN = %d signature[%d] = %x", P.XLEN, i, signature[i]);
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end
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// Check errors
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errors = (i == SIGNATURESIZE+1); // error if file is empty
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i = 0;
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testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
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testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
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/* verilator lint_off INFINITELOOP */
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/* verilator lint_off WIDTHXZEXPAND */
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while (signature[i] !== 'bx) begin
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/* verilator lint_on WIDTHXZEXPAND */
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for (i=0; i<sigentries; i++) begin
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logic [P.XLEN-1:0] sig;
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// **************************************
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// ***** BUG BUG BUG make sure RT undoes this.
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@ -560,21 +585,12 @@ module testbench;
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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//$display(" Error on test %s result %d: adr = %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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// TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
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$stop; //***debug
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$stop;
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end
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i = i + 1;
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) begin
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$display("%s succeeded. Brilliant!!!", TestName);
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end else begin
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$display("%s failed with %d errors. :(", TestName, errors);
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//totalerrors = totalerrors+1;
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end
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endtask //
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if (errors) $display("%s failed with %d errors. :(", TestName, errors);
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else $display("%s succeeded. Brilliant!!!", TestName);
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endtask
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/* verilator lint_on WIDTHTRUNC */
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/* verilator lint_on WIDTHEXPAND */
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@ -596,7 +612,6 @@ task automatic updateProgramAddrLabelArray;
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ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
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if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
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// *** RT: I'm a bit confused by the required initialization here.
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ProgramAddrLabelArray["begin_signature"] = 0;
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ProgramAddrLabelArray["tohost"] = 0;
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ProgramAddrLabelArray["sig_end_canary"] = 0;
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@ -609,7 +624,7 @@ task automatic updateProgramAddrLabelArray;
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end
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end
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if(ProgramAddrLabelArray["begin"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
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if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
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if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);
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$fclose(ProgramLabelMapFP);
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@ -13,7 +13,7 @@
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00000001 # delay 1
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00080000 # fmt
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00000000 # tx_data
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00000000 # tx_mark
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@ -23,7 +23,7 @@
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00000000 # ie reset
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00000000 # ip reset
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00000000 # fifo watermark and edge case tests
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00000001
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@ -249,7 +249,7 @@
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00000000 #read mip
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00000000 #read tx ip
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00000022 #clear 1 frame from rx fifo
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00000000 # read recieve ip
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