From 167e061a1caadd393da1cb0c7e03b6ad00fbe5c5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 6 Jan 2024 08:19:46 -0800 Subject: [PATCH 1/5] Fixed truncated begin_signature in testbench --- testbench/testbench.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 7b5877e9c..5b5e905ea 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -588,7 +588,6 @@ task automatic updateProgramAddrLabelArray; ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r"); if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files - // *** RT: I'm a bit confused by the required initialization here. ProgramAddrLabelArray["begin_signature"] = 0; ProgramAddrLabelArray["tohost"] = 0; ProgramAddrLabelArray["sig_end_canary"] = 0; @@ -601,7 +600,7 @@ task automatic updateProgramAddrLabelArray; end end - if(ProgramAddrLabelArray["begin"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile); + if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile); if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile); $fclose(ProgramLabelMapFP); From 4a4a7b0d0313b23b39a0552eb9054f87c913ed58 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 6 Jan 2024 18:55:57 -0800 Subject: [PATCH 2/5] Back to SweRVe Makefile flags for CoreMark --- benchmarks/coremark/Makefile | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index 81c2b0959..db8a6e1d6 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -11,11 +11,13 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \ $(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \ $(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32) +ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbc_zbs #ARCH := rv$(XLEN)gc_zba_zbb_zbc_zbs #ARCH := rv$(XLEN)gc -ARCH := rv$(XLEN)imc_zicsr +#ARCH := rv$(XLEN)imc_zicsr #ARCH := rv$(XLEN)im_zicsr #ARCH := rv$(XLEN)i_zicsr + PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \ -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \ @@ -23,6 +25,24 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ -nostdlib -nostartfiles -ffreestanding -mstrict-align \ -DTOTAL_DATA_SIZE=2000 -DMAIN_HAS_NOARGC=1 -DPERFORMANCE_RUN=1 -DITERATIONS=10 -DXLEN=$(XLEN) +# Black Parrott +#PORT_CFLAGS = -O2 -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4 \ + -DITERATIONS=10 -DPERFORMANCE_RUN=1 +#OPTIMIZE := -O2 -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4 +#override CFLAGS += $(OPTIMIZE) -DFLAGS_STR=\""$(OPTIMIZE)"\" +#override CFLAGS += -DITERATIONS=10 -DPERFORMANCE_RUN=1 + +# try adding the new fields from muntjac coremark build +#PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ + -fno-common -flto -funswitch-loops -mcmodel=medany \ + -falign-functions=4 -falign-jumps=4 -falign-loops=4 \ + -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions --param max-inline-insns-auto=20 -falign-jumps=4 \ + -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \ + -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta \ + -nostdlib -nostartfiles -ffreestanding -mstrict-align \ + -DTOTAL_DATA_SIZE=2000 -DMAIN_HAS_NOARGC=1 -DPERFORMANCE_RUN=1 -DITERATIONS=10 -DXLEN=$(XLEN) + + all: $(work_dir)/coremark.bare.riscv.elf.memfile run: From caedab679a098cb5e4100b8c00ce65759ae8c4fc Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 7 Jan 2024 07:14:12 -0800 Subject: [PATCH 3/5] Rewrote testbench to count signature entries rather than looking for x; this will facilitate Verilator which does not use x --- testbench/testbench.sv | 93 ++++++++++--------- .../references/WALLY-spi-01.reference_output | 6 +- 2 files changed, 54 insertions(+), 45 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index be2df5a59..29b5207a0 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -388,11 +388,10 @@ module testbench; end end - // *** 06 January 2024 RT: may have to uncomment this block for vcs/verilator integer adrindex; if (P.UNCORE_RAM_SUPPORTED) always @(posedge clk) - if (ResetMem) // program memory is sometimes reset + if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory) for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; @@ -442,6 +441,15 @@ module testbench; clk = 1; # 5; clk = 0; # 5; end + /* + // Print key info each cycle for debugging + always @(posedge clk) begin + #2; + $display("PCM: %x InstrM: %x (%5s) WriteDataM: %x IEUResultM: %x", + dut.core.PCM, dut.core.InstrM, InstrMName, dut.core.WriteDataM, dut.core.ieu.dp.IEUResultM); + end + */ + //////////////////////////////////////////////////////////////////////////////// // Support logic //////////////////////////////////////////////////////////////////////////////// @@ -504,6 +512,9 @@ module testbench; input logic riscofTest; input integer begin_signature_addr; output integer errors; + int fd, code; + string line; + int siglines, sigentries; localparam SIGNATURESIZE = 5000000; integer i; @@ -512,41 +523,48 @@ module testbench; string signame; logic [P.XLEN-1:0] testadr, testadrNoBase; - // for tests with no self checking mechanism, read .signature.output file and compare to check for errors - // clear signature to prevent contamination from previous tests - for(i=0; i 1) begin // skip blank lines + if ($sscanf(line, "%x", sig32[siglines])) siglines = siglines + 1; // increment if line is not blank + end end + $fclose(fd); end + // Check valid number of lines were read + if (siglines == 0) begin + errors = 1; + $display("Error: empty test file %s", signame); + end else if (P.XLEN == 64 & (siglines % 2)) begin + errors = 1; + $display("Error: RV64 signature has odd number of lines %s", signame); + end else errors = 0; + + // copy lines into signature, converting to XLEN if necessary + sigentries = (P.XLEN == 32) ? siglines : siglines/2; // number of signature entries + for (i=0; i Date: Sun, 7 Jan 2024 09:00:19 -0800 Subject: [PATCH 4/5] Updated testbench to count size of signature without searching for x. Now runs with Verilator. --- testbench/testbench.sv | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 29b5207a0..b169cece9 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -519,6 +519,7 @@ module testbench; localparam SIGNATURESIZE = 5000000; integer i; logic [31:0] sig32[0:SIGNATURESIZE]; + logic [31:0] parsed; logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; string signame; logic [P.XLEN-1:0] testadr, testadrNoBase; @@ -535,17 +536,25 @@ module testbench; else begin while (!$feof(fd)) begin code = $fgets(line, fd); - if (!code) begin + if (code != 0) begin int errno; string errstr; errno = $ferror(fd, errstr); - if (errno) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr); - end else if (line.len() > 1) begin // skip blank lines - if ($sscanf(line, "%x", sig32[siglines])) siglines = siglines + 1; // increment if line is not blank + if (errno != 0) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr); + if (line.len() > 1) begin // skip blank lines +// if ($sscanf(line, "%x", sig32[siglines])) siglines = siglines + 1; // increment if line is not blank + if ($sscanf(line, "%x", parsed) != 0) begin + sig32[siglines] = parsed; +// $display("line = %s len = %d sig32[%d] = %x", line, line.len(), siglines, sig32[siglines]); + siglines = siglines + 1; // increment if line is not blank + end + end end end $fclose(fd); end +// for(i=0; i Date: Sun, 7 Jan 2024 21:30:33 -0800 Subject: [PATCH 5/5] Verilate running (slowly) --- sim/verilate | 43 +++++++++++++++++++++++++++++++----------- testbench/testbench.sv | 4 ---- 2 files changed, 32 insertions(+), 15 deletions(-) diff --git a/sim/verilate b/sim/verilate index 6d60a5f26..23eb115e1 100755 --- a/sim/verilate +++ b/sim/verilate @@ -1,21 +1,42 @@ #!/bin/bash # simulate with Verilator -# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes -# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes - export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. #for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do -for config in rv64gc; do - echo "$config simulating..." - # not working: -GTEST="arch64i" - if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"arch64i\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then - echo "Exiting after $config lint due to errors or warnings" - exit 1 - fi - ./obj_dir/Vtestbench + +# define associateive array of tests to run +declare -A suites +rv64gccases=("arch64zba" "arch64zbb" "arch64zbc" "arch64zbs" "arch64i" "arch64m" "arch64a" "arch64f" "arch64d" "arch64c" "arch64f_fma" "arch64d_fma" "wally64priv") +suites["rv64gc"]=${rv64gccases[@]} +rv64icases=("arch64i") +suites["rv64i"]=${rv32icases[@]} +rv32gccases=("arch32zba" "arch32zbb" "arch32zbc" "arch32zbs" "arch32i" "arch32m" "arch32a" "arch32f" "arch32d" "arch32c" "arch64f_fma" "arch64d_fma" "wally32priv") +suites["rv32gc"]=${rv32gccases[@]} +rv32imccases=("arch32i" "arch32m" "arch32c") +suites["rv32imc"]=${rv32imccases[@]} +rv32icases=("arch32i") +suites["rv32i"]=${rv32icases[@]} +rv32ecases=("arch32e") +suites["rv32e"]=${rv32ecases[@]} + +for config in ${!suites[@]}; do + for suite in ${suites[${config}]}; do + echo "Verilating ${config} ${suite}" + if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"${suite}\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + echo "Exiting after ${config} ${suite} verilation due to errors or warnings" + exit 1 + fi + ./obj_dir/Vtestbench + done done echo "Verilation complete" + +# command line to invoke Verilator on rv64gc arch64i +# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes + +# command line with debugging to address core dumps +# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes + diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b169cece9..3910c1cfd 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -542,10 +542,8 @@ module testbench; errno = $ferror(fd, errstr); if (errno != 0) $display("Error %d (code %d) reading line %d of %s: %s", errno, code, siglines, signame, errstr); if (line.len() > 1) begin // skip blank lines -// if ($sscanf(line, "%x", sig32[siglines])) siglines = siglines + 1; // increment if line is not blank if ($sscanf(line, "%x", parsed) != 0) begin sig32[siglines] = parsed; -// $display("line = %s len = %d sig32[%d] = %x", line, line.len(), siglines, sig32[siglines]); siglines = siglines + 1; // increment if line is not blank end end @@ -553,8 +551,6 @@ module testbench; end $fclose(fd); end -// for(i=0; i