From 09c92a6b5d4eee75a5888da46e59b02f13f5c9f0 Mon Sep 17 00:00:00 2001
From: Noah Boorstin <nboorstin@hmc.edu>
Date: Mon, 25 Jan 2021 20:06:13 -0500
Subject: [PATCH] Fixed mem write checking

now passes around 50 instructions!
---
 wally-pipelined/regression/wally-busybear.do    |  3 ++-
 wally-pipelined/testbench/testbench-busybear.sv | 10 +++++++---
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do
index cd834b6af..50c716ed1 100644
--- a/wally-pipelined/regression/wally-busybear.do
+++ b/wally-pipelined/regression/wally-busybear.do
@@ -53,6 +53,7 @@ add wave -hex /testbench_busybear/MemRWM[0]
 add wave -hex /testbench_busybear/MemRWM[1]
 add wave -hex /testbench_busybear/ByteMaskM
 add wave -hex /testbench_busybear/WriteDataM
+add wave -hex /testbench_busybear/DataAdrM
 add wave -hex /testbench_busybear/dut/dp/regf/rf[1]
 add wave -hex /testbench_busybear/dut/dp/regf/rf[2]
 add wave -hex /testbench_busybear/dut/dp/regf/rf[3]
@@ -128,6 +129,6 @@ add wave /testbench_busybear/InstrWName
 #set DefaultRadix hexadecimal
 #
 #-- Run the Simulation 
-run 700
+run 800
 #run -all
 ##quit
diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index fd41f9d3b..b76f4c928 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -103,14 +103,18 @@ module testbench_busybear();
     end
   end
 
-  logic [`XLEN-1:0] writeDataExpected;
+  logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
   // this might need to change
   always @(WriteDataM or DataAdrM or ByteMaskM) begin
+    #1;
     if (MemRWM[0]) begin
-      $display("!!!!");
       scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
+      scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
       if (writeDataExpected != WriteDataM) begin
-        $display("%t ps: WriteDataM does not equal WriteDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
+        $display("%t ps: WriteDataM does not equal writeDataExpected: %x, %x", $time, WriteDataM, writeDataExpected);
+      end
+      if (writeAdrExpected != DataAdrM) begin
+        $display("%t ps: DataAdrM does not equal writeAdrExpected: %x, %x", $time, DataAdrM, writeAdrExpected);
       end
     end
   end