From 09c4aaa5d9b3d427658ee423214f5a5d15d3841b Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Thu, 26 Oct 2023 20:14:14 -0700
Subject: [PATCH] Fixed reporting of timing on modules with wrappers

---
 synthDC/scripts/synth.tcl | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 997574312..3e616e130 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -257,6 +257,19 @@ set write_hier 1        ;# generate hierarchy report
 if { $wrapper == 1 } {
     set designname [format "%s%s" $my_design "__*"]
     current_design $designname
+
+    # recreate clock below wrapper level or reporting doesn't work properly
+    set find_clock [ find port [list $my_clock_pin] ]
+    if {  $find_clock != [list] } {
+        echo "Found clock!"
+        set my_clk $my_clock_pin
+        create_clock -period $my_period $my_clk
+        set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
+    } else {
+        echo "Did not find clock! Design is probably combinational!"
+        set my_clk vclk
+        create_clock -period $my_period -name $my_clk
+    }
 } 
 
 # Report Constraint Violators