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https://github.com/openhwgroup/cvw
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added test cases
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@ -27,7 +27,6 @@
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// Current limitations: Flash read sequencer mode not implemented, dual and quad modes untestable with current test plan.
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// Current limitations: Flash read sequencer mode not implemented, dual and quad modes untestable with current test plan.
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// Hardware interlock change to busy signal
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// Hardware interlock change to busy signal
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// Get rid of dual/ quad mode
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// write tests for fifo full and empty watermark edge cases
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// write tests for fifo full and empty watermark edge cases
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// HoldModeDeassert make sure still works
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// HoldModeDeassert make sure still works
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// Comment on FIFOs: watermark calculations
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// Comment on FIFOs: watermark calculations
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@ -423,7 +422,7 @@ module SynchFIFO #(parameter M =3 , N= 8)(
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output logic wwatermark, rwatermark);
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output logic wwatermark, rwatermark);
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logic [N-1:0] mem[2**M];
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logic [N-1:0] mem[2**M];
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logic [M:0] rwpr, wptr;
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logic [M:0] rptr, wptr;
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logic [M:0] rptrnext, wptrnext;
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logic [M:0] rptrnext, wptrnext;
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logic rempty_val;
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logic rempty_val;
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logic wfull_val;
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logic wfull_val;
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