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	Fixed brom name
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				@ -116,9 +116,9 @@ module ahblite (
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  assign HADDR = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0];
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					  assign HADDR = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0];
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  assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits
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					  assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits
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  assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst.
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					  assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst.
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  assign HPROT = 4'b0011; // not used; see Section 3.7
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  assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
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					  assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
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  assign HMASTLOCK = 0; // no locking supported
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					   assign HPROT = 4'b0011; // not used; see Section 3.7
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					 assign HMASTLOCK = 0; // no locking supported
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  assign HWRITE = (NextBusState == MEMWRITE);
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					  assign HWRITE = (NextBusState == MEMWRITE);
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  // Byte mask for HWSTRB
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					  // Byte mask for HWSTRB
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  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB));
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					  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB));
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@ -40,7 +40,7 @@ module irom(
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  localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
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					  localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
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  localparam OFFSET = $clog2(`LLEN/8);
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					  localparam OFFSET = $clog2(`LLEN/8);
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  brom1p1rw #(ADDR_WDITH, 32) 
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					  brom1p1r #(ADDR_WDITH, 32) 
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    rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
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					    rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
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endmodule  
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					endmodule  
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