diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv
index e619a50db..e2606b10f 100644
--- a/pipelined/src/ebu/ahblite.sv
+++ b/pipelined/src/ebu/ahblite.sv
@@ -116,9 +116,9 @@ module ahblite (
   assign HADDR = LSUGrant ? LSUHADDR[31:0] : IFUHADDR[31:0];
   assign HSIZE = LSUGrant ? {1'b0, LSUHSIZE[1:0]} : 3'b010; // Instruction reads are always 32 bits
   assign HBURST = LSUGrant ? LSUHBURST : IFUHBURST; // If doing memory accesses, use LSUburst, else use Instruction burst.
-  assign HPROT = 4'b0011; // not used; see Section 3.7
   assign HTRANS = LSUGrant ? LSUHTRANS : IFUHTRANS; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
-  assign HMASTLOCK = 0; // no locking supported
+   assign HPROT = 4'b0011; // not used; see Section 3.7
+ assign HMASTLOCK = 0; // no locking supported
   assign HWRITE = (NextBusState == MEMWRITE);
   // Byte mask for HWSTRB
   swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB));
diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv
index 83585c07e..2670511e1 100644
--- a/pipelined/src/ifu/irom.sv
+++ b/pipelined/src/ifu/irom.sv
@@ -40,7 +40,7 @@ module irom(
   localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
   localparam OFFSET = $clog2(`LLEN/8);
 
-  brom1p1rw #(ADDR_WDITH, 32) 
+  brom1p1r #(ADDR_WDITH, 32) 
     rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
 endmodule