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Merge branch 'dev' into installation

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This commit is contained in:
Jordan Carlin 2024-07-02 21:55:21 -07:00
commit 045bdddfde
6 changed files with 191 additions and 184 deletions
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18
bin/regression-wally
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@ -313,8 +313,8 @@ os.chdir(regressionDir)
coveragesim = "questa" # Questa is required for code/functional coverage coveragesim = "questa" # Questa is required for code/functional coverage
#defaultsim = "vcs" # Default simulator for all other tests; change to Verilator when flow is ready #defaultsim = "vcs" # Default simulator for all other tests; change to Verilator when flow is ready
defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready #defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
#defaultsim = "verilator" # Default simulator for all other tests defaultsim = "verilator" # Default simulator for all other tests
coverage = '--coverage' in sys.argv coverage = '--coverage' in sys.argv
fp = '--fp' in sys.argv fp = '--fp' in sys.argv
@ -323,9 +323,8 @@ testfloat = '--testfloat' in sys.argv
if (nightly): if (nightly):
nightMode = "--nightly"; nightMode = "--nightly";
# sims = [defaultsim] # sims = [defaultsim] # uncomment to use only the default simulator
sims = ["questa", "vcs"] sims = ["questa", "verilator", "vcs"] # uncomment to exercise all simulators
# sims = ["questa", "verilator", "vcs"] # *** uncomment to exercise all simulators
else: else:
nightMode = "" nightMode = ""
sims = [defaultsim] sims = [defaultsim]
@ -352,6 +351,7 @@ if (coverage): # only run RV64GC tests on Questa in coverage mode
addTests(tests64gc_fp, "questa") addTests(tests64gc_fp, "questa")
else: else:
for sim in sims: for sim in sims:
addTests(tests_buildrootshort, sim)
addTests(tests, sim) addTests(tests, sim)
addTests(tests64gc_nofp, sim) addTests(tests64gc_nofp, sim)
addTests(tests64gc_fp, sim) addTests(tests64gc_fp, sim)
@ -359,10 +359,7 @@ else:
# run derivative configurations in nightly regression # run derivative configurations in nightly regression
if (nightly): if (nightly):
# addTests(tests_buildrootboot, defaultsim) # addTests(tests_buildrootboot, defaultsim)
addTests(tests_buildrootshort, defaultsim)
addTests(derivconfigtests, defaultsim) addTests(derivconfigtests, defaultsim)
else:
addTests(tests_buildrootshort, defaultsim)
# testfloat tests # testfloat tests
if (testfloat): # for testfloat alone, just run testfloat tests if (testfloat): # for testfloat alone, just run testfloat tests
@ -433,9 +430,10 @@ def main():
"""Run the tests and count the failures""" """Run the tests and count the failures"""
global configs, coverage global configs, coverage
os.chdir(regressionDir) os.chdir(regressionDir)
os.system('rm -rf questa/wkdir') dirs = ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]
for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]: for d in dirs:
try: try:
os.system('rm -rf %s' % d)
os.mkdir(d) os.mkdir(d)
except: except:
pass pass

91
bin/wsim
View File

@ -14,38 +14,16 @@
import argparse import argparse
import os import os
def LaunchSim(ElfFile):
# Launch selected simulator def LaunchSim(ElfFile, flags):
cd = "cd $WALLY/sim/" +args.sim cd = "cd $WALLY/sim/" +args.sim
# ugh. can't have more than 9 arguments passed to vsim. why? I'll have to remove --lockstep when running
# functional coverage and imply it. # per-simulator launch
if (args.sim == "questa"): if (args.sim == "questa"):
if (args.lockstep): # Questa cannot accept more than 9 arguments. fcov implies lockstep
prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic"
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0
if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
else: ImperasPlusArgs = ""
if(args.fcov):
CovEnableStr = "1" if int(args.covlog) > 0 else "0";
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr;
suffix = ""
else:
CovEnableStr = ""
suffix = "--lockstep"
else:
prefix = ""
ImperasPlusArgs = ""
suffix = ""
if (args.tb == "testbench_fp"): if (args.tb == "testbench_fp"):
args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args
cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + suffix + " " + ImperasPlusArgs cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + flags
if (args.coverage):
cmd += " --coverage"
if (args.fcov):
cmd += " --fcov"
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
if(args.tb == "testbench"): if(args.tb == "testbench"):
cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc -GDEBUG=1\"" cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc -GDEBUG=1\""
@ -58,24 +36,20 @@ def LaunchSim(ElfFile):
elif (args.sim == "verilator"): elif (args.sim == "verilator"):
# PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i
print(f"Running Verilator on {args.config} {args.testsuite}") print(f"Running Verilator on {args.config} {args.testsuite}")
if (args.coverage):
print("Coverage option not available for Verilator")
exit(1)
if (args.gui):
print("GUI option not available for Verilator")
exit(1)
os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} EXTRA_ARGS='{args.args}'") os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} EXTRA_ARGS='{args.args}'")
elif (args.sim == "vcs"): elif (args.sim == "vcs"):
print(f"Running VCS on " + args.config + " " + args.testsuite) print(f"Running VCS on " + args.config + " " + args.testsuite)
if (args.gui): if (args.gui):
args.args += "gui" args.args += "gui"
elif (args.coverage): cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.args + " " + flags
args.args += "coverage"
cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.args
print(cmd) print(cmd)
os.system(cmd) os.system(cmd)
########################
# main wsim script
########################
# Parse arguments # Parse arguments
parser = argparse.ArgumentParser() parser = argparse.ArgumentParser()
parser.add_argument("config", help="Configuration file") parser.add_argument("config", help="Configuration file")
@ -96,6 +70,7 @@ print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim
ElfFile="" ElfFile=""
DirectorMode = 0 DirectorMode = 0
ElfList = [] ElfList = []
WALLY = os.environ.get('WALLY')
if(os.path.isfile(args.testsuite)): if(os.path.isfile(args.testsuite)):
ElfFile = "+ElfFile=" + args.testsuite ElfFile = "+ElfFile=" + args.testsuite
@ -111,21 +86,43 @@ elif(os.path.isdir(args.testsuite)):
print(ElfList) print(ElfList)
# Validate arguments # Validate arguments
if (args.gui): if (args.gui or args.coverage or args.fcov or args.lockstep):
if args.sim not in ["questa", "vcs"]: if args.sim not in ["questa", "vcs"]:
print("GUI option only supported for Questa and VCS") print("Option only supported for Questa and VCS")
exit(1)
if (args.coverage):
if args.sim not in ["questa", "vcs"]:
print("Coverage option only available for Questa and VCS")
exit(1) exit(1)
if (args.vcd): if (args.vcd):
args.args += " -DMAKEVCD=1" args.args += " -DMAKEVCD=1"
# if lockstep is enabled, then we need to pass the Imperas lockstep arguments
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0
if (args.lockstep):
prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic"
if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
else: ImperasPlusArgs = ""
if(args.fcov):
CovEnableStr = "1" if int(args.covlog) > 0 else "0";
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr;
suffix = ""
else:
CovEnableStr = ""
suffix = "--lockstep"
else:
prefix = ""
ImperasPlusArgs = ""
suffix = ""
flags = suffix + " " + ImperasPlusArgs
# other flags
if (args.coverage):
flags += " --coverage"
if (args.fcov):
flags += " --fcov"
# create the output sub-directories. # create the output sub-directories.
WALLY = os.environ.get('WALLY')
regressionDir = WALLY + '/sim/' regressionDir = WALLY + '/sim/'
for d in ["logs", "wkdir", "cov"]: for d in ["logs", "wkdir", "cov"]:
try: try:
@ -135,7 +132,7 @@ for d in ["logs", "wkdir", "cov"]:
if(DirectorMode): if(DirectorMode):
for ElfFile in ElfList: for ElfFile in ElfList:
LaunchSim(ElfFile) LaunchSim(ElfFile, flags)
else: else:
LaunchSim(ElfFile) LaunchSim(ElfFile, flags)

4
config/derivlist.txt
View File

@ -814,11 +814,13 @@ deriv f_rv32gc rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0 ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
ZCD_SUPPORTED 0
deriv fh_rv32gc rv32gc deriv fh_rv32gc rv32gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0 ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
ZCD_SUPPORTED 0
deriv fd_rv32gc rv32gc deriv fd_rv32gc rv32gc
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
@ -838,11 +840,13 @@ deriv f_rv64gc rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0 ZCD_SUPPORTED 0
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0
ZCD_SUPPORTED 0
deriv fh_rv64gc rv64gc deriv fh_rv64gc rv64gc
D_SUPPORTED 0 D_SUPPORTED 0
ZCD_SUPPORTED 0 ZCD_SUPPORTED 0
ZFH_SUPPORTED 1 ZFH_SUPPORTED 1
ZCD_SUPPORTED 0
deriv fd_rv64gc rv64gc deriv fd_rv64gc rv64gc
ZFH_SUPPORTED 0 ZFH_SUPPORTED 0

29
sim/vcs/run_vcs
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@ -90,29 +90,28 @@ RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/
# Simulation and Coverage Commands # Simulation and Coverage Commands
OUTPUT="sim_out" OUTPUT="sim_out"
VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn ${INCLUDE_PATH} $RTL_FILES" VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn ${INCLUDE_PATH} " # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson
SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS}" SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS} -no_save"
COV_FILES="${TB}/coverage/test_pmp_coverage.sv"
COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE"
### CODE COVERAGE REPORT in IndividualCovReport in XML format
#COV_RUN="urg -dir ${WKDIR}/COVERAGE.vdb -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}"
### CODE COVERAGE REPORT in IndividualCovReport in text format
COV_RUN="urg -dir ./${WKDIR}/COVERAGE.vdb -format text -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}"
# Clean and run simulation with VCS # Clean and run simulation with VCS
if [ "$3" = "coverage" ]; then if [ "$3" = "--coverage" ]; then
echo -e "${YELLOW}#### Running VCS Simulation with Coverage ####${NC}" echo -e "${YELLOW}#### Running VCS Simulation with Coverage ####${NC}"
# Code Coverage. COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE"
$VCS_CMD -Mdir=${WKDIR} $COV_OPTIONS -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log" COV_RUN="urg -dir ./${WKDIR}/COVERAGE.vdb -format text -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}"
$SIMV_CMD $COV_OPTIONS $VCS_CMD -Mdir=${WKDIR} $COV_OPTIONS $RTL_FILES -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
$SIMV_CMD $COV_OPTIONS # dh 6/27/24 *** are COV_OPTIONS really needed?
$COV_RUN $COV_RUN
#cp -rf urgReport $COV #cp -rf urgReport $COV
elif [ "$3" = "--lockstep" ]; then
echo -e "${YELLOW}#### Running VCS Simulation with Lockstep ####${NC}"
LOCKSTEP_OPTIONS=" +define+USE_IMPERAS_DV +incdir+${IMPERAS_HOME}/ImpPublic/include/host +incdir+${IMPERAS_HOME}/ImpProprietary/include/host ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv ${TB}/common/wallyTracer.sv"
LOCKSTEP_SIMV="-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model"
$VCS_CMD -Mdir=${WKDIR} $LOCKSTEP_OPTIONS $RTL_FILES -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
$SIMV_CMD $LOCKSTEP_SIMV
else else
echo -e "${YELLOW}#### Running VCS Simulation ####${NC}" echo -e "${YELLOW}#### Running VCS Simulation ####${NC}"
$VCS_CMD -Mdir=${WKDIR} -o ${WKDIR}/$OUTPUT -work ${WKDIR} -Mlib ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log" $VCS_CMD -Mdir=${WKDIR} $RTL_FILES -o ${WKDIR}/$OUTPUT -work ${WKDIR} -Mlib ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
$SIMV_CMD $SIMV_CMD
fi fi

226
testbench/testbench_fp.sv
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@ -66,6 +66,7 @@ module testbench_fp;
logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit
logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res
logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags
logic [4:0] CmpFlg; // Outputed flags logic [4:0] CmpFlg; // Outputed flags
logic AnsNaN, ResNaN, NaNGood; logic AnsNaN, ResNaN, NaNGood;
@ -820,13 +821,14 @@ module testbench_fp;
end end
always_comb begin always_comb begin
FpResExtended = {{(P.Q_LEN-P.FLEN){1'b1}}, FpRes};
// select the result to check // select the result to check
case (UnitVal) case (UnitVal)
`FMAUNIT: Res = FpRes; `FMAUNIT: Res = FpResExtended;
`DIVUNIT: Res = FpRes; `DIVUNIT: Res = FpResExtended;
`CMPUNIT: Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, CmpRes}; `CMPUNIT: Res = {{(Q_LEN-XLEN){1'b0}}, CmpRes};
`CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, IntRes}; else Res = FpRes; `CVTINTUNIT: if (WriteIntVal) Res = {{(Q_LEN-XLEN){1'b0}}, IntRes}; else Res = FpResExtended;
`CVTFPUNIT: Res = FpRes; `CVTFPUNIT: Res = FpResExtended;
endcase endcase
// select the flag to check // select the flag to check
@ -965,7 +967,7 @@ module testbench_fp;
/////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////
// check if result is correct // check if result is correct
assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); assign ResMatch = ((Res[P.FLEN-1:0] === Ans[P.FLEN-1:0]) | NaNGood | (NaNGood === 1'bx));
assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
assign FMAop = (OpCtrlVal == `FMAUNIT); assign FMAop = (OpCtrlVal == `FMAUNIT);
@ -987,7 +989,7 @@ module testbench_fp;
// increment the test // increment the test
TestNum += 1; TestNum += 1;
// clear the vectors // clear the vectors
for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}}; for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = {P.Q_LEN*4+8{1'bx}};
// read next files // read next files
$readmemh({`PATH, Tests[TestNum]}, TestVectors); $readmemh({`PATH, Tests[TestNum]}, TestVectors);
// set the vector index back to 0 // set the vector index back to 0
@ -1052,6 +1054,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
// Format of vectors Inputs(1/2/3)_AnsFlg // Format of vectors Inputs(1/2/3)_AnsFlg
always @(VectorNum) begin always @(VectorNum) begin
AnsFlg = TestVector[4:0]; AnsFlg = TestVector[4:0];
//$display("Entering readvectors with VectorNum=%d, TestVector=%x, Unit=%d, Fmt=%d, OpCtrl=%d", VectorNum, TestVector, Unit, Fmt, OpCtrl);
case (Unit) case (Unit)
`FMAUNIT: `FMAUNIT:
case (Fmt) case (Fmt)
@ -1070,48 +1073,49 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
end end
2'b01: if (P.D_SUPPORTED) begin // double 2'b01: if (P.D_SUPPORTED) begin // double
if (OpCtrl === `FMA_OPCTRL) begin if (OpCtrl === `FMA_OPCTRL) begin
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]};
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]}; Z = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]};
$display("Read %x %x %x", X, Y, Z);
end end
else begin else begin
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
else Y = {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)}; else Y = {{P.Q_LEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)};
if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}}; if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}};
else Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; else Z = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
end end
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b00: if (P.F_SUPPORTED) begin // single 2'b00: if (P.F_SUPPORTED) begin // single
if (OpCtrl === `FMA_OPCTRL) begin if (OpCtrl === `FMA_OPCTRL) begin
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]};
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]}; Z = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]};
end end
else begin else begin
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]}; if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
else Y = {{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)}; else Y = {{P.Q_LEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)};
if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}}; if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}};
else Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]}; else Z = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
end end
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b10: begin // half 2'b10: begin // half
if (OpCtrl === `FMA_OPCTRL) begin if (OpCtrl === `FMA_OPCTRL) begin
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]};
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]}; Z = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]};
end end
else begin else begin
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
else Y = {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)}; else Y = {{P.Q_LEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)};
if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}}; if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}};
else Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; else Z = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
end end
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
endcase endcase
`DIVUNIT: `DIVUNIT:
@ -1122,16 +1126,16 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
Ans = TestVector[8+(P.Q_LEN-1):8]; Ans = TestVector[8+(P.Q_LEN-1):8];
end end
2'b01: if (P.D_SUPPORTED) begin // double 2'b01: if (P.D_SUPPORTED) begin // double
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b00: if (P.F_SUPPORTED) begin // single 2'b00: if (P.F_SUPPORTED) begin // single
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b10: begin // half 2'b10: begin // half
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
endcase endcase
else else
@ -1142,19 +1146,19 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
Ans = TestVector[8+(P.Q_LEN-1):8]; Ans = TestVector[8+(P.Q_LEN-1):8];
end end
2'b01: if (P.D_SUPPORTED) begin // double 2'b01: if (P.D_SUPPORTED) begin // double
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]}; Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b00: if (P.F_SUPPORTED) begin // single 2'b00: if (P.F_SUPPORTED) begin // single
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]}; Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b10: begin // half 2'b10: begin // half
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]}; Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
endcase endcase
`CMPUNIT: `CMPUNIT:
@ -1162,22 +1166,22 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
2'b11: begin // quad 2'b11: begin // quad
X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)]; X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)];
Y = TestVector[12+(P.Q_LEN)-1:12]; Y = TestVector[12+(P.Q_LEN)-1:12];
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
end end
2'b01: if (P.D_SUPPORTED) begin // double 2'b01: if (P.D_SUPPORTED) begin // double
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]}; Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
end end
2'b00: if (P.F_SUPPORTED) begin // single 2'b00: if (P.F_SUPPORTED) begin // single
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]}; Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
end end
2'b10: begin // half 2'b10: begin // half
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]}; Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]}; Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
end end
endcase endcase
`CVTFPUNIT: `CVTFPUNIT:
@ -1190,75 +1194,75 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
end end
2'b01: if (P.D_SUPPORTED) begin // double 2'b01: if (P.D_SUPPORTED) begin // double
X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]}; X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]};
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b00: begin // single 2'b00: begin // single
X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]}; X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]};
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b10: begin // half 2'b10: begin // half
X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]}; X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]};
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
endcase endcase
end end
2'b01: if (P.D_SUPPORTED) begin // double 2'b01: if (P.D_SUPPORTED) begin // double
case (OpCtrl[1:0]) case (OpCtrl[1:0])
2'b11: begin // quad 2'b11: begin // quad
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
Ans = TestVector[8+(P.Q_LEN-1):8]; Ans = TestVector[8+(P.Q_LEN-1):8];
end end
2'b01: begin // double 2'b01: begin // double
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]};
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b00: begin // single 2'b00: begin // single
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]};
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b10: begin // half 2'b10: begin // half
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]};
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
endcase endcase
end end
2'b00: if (P.F_SUPPORTED) begin // single 2'b00: if (P.F_SUPPORTED) begin // single
case (OpCtrl[1:0]) case (OpCtrl[1:0])
2'b11: begin // quad 2'b11: begin // quad
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
Ans = TestVector[8+(P.Q_LEN-1):8]; Ans = TestVector[8+(P.Q_LEN-1):8];
end end
2'b01: if (P.D_SUPPORTED) begin // double 2'b01: if (P.D_SUPPORTED) begin // double
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]};
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b00: begin // single 2'b00: begin // single
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]};
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b10: begin // half 2'b10: begin // half
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]};
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
endcase endcase
end end
2'b10: begin // half 2'b10: begin // half
case (OpCtrl[1:0]) case (OpCtrl[1:0])
2'b11: begin // quad 2'b11: begin // quad
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
Ans = TestVector[8+(P.Q_LEN-1):8]; Ans = TestVector[8+(P.Q_LEN-1):8];
end end
2'b01: if (P.D_SUPPORTED) begin // double 2'b01: if (P.D_SUPPORTED) begin // double
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]};
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b00: if (P.F_SUPPORTED) begin // single 2'b00: if (P.F_SUPPORTED) begin // single
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]};
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b10: begin // half 2'b10: begin // half
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]};
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
endcase endcase
end end
@ -1269,25 +1273,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
// {is the integer a long, is the opperation to an integer} // {is the integer a long, is the opperation to an integer}
casez ({OpCtrl[2:1]}) casez ({OpCtrl[2:1]})
2'b11: begin // long -> quad 2'b11: begin // long -> quad
X = {P.FLEN{1'bx}}; X = {P.Q_LEN{1'bx}};
SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)]; SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
Ans = TestVector[8+(P.Q_LEN-1):8]; Ans = TestVector[8+(P.Q_LEN-1):8];
end end
2'b10: begin // int -> quad 2'b10: begin // int -> quad
// correctly sign extend the integer depending on if it's a signed/unsigned test // correctly sign extend the integer depending on if it's a signed/unsigned test
X = {P.FLEN{1'bx}}; X = {P.Q_LEN{1'bx}};
SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]}; SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]};
Ans = TestVector[8+(P.Q_LEN-1):8]; Ans = TestVector[8+(P.Q_LEN-1):8];
end end
2'b01: begin // quad -> long 2'b01: begin // quad -> long
X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
end end
2'b00: begin // quad -> int 2'b00: begin // quad -> int
X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]};
end end
endcase endcase
end end
@ -1295,25 +1299,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
// {Int->Fp?, is the integer a long} // {Int->Fp?, is the integer a long}
casez ({OpCtrl[2:1]}) casez ({OpCtrl[2:1]})
2'b11: begin // long -> double 2'b11: begin // long -> double
X = {P.FLEN{1'bx}}; X = {P.Q_LEN{1'bx}};
SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)]; SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b10: begin // int -> double 2'b10: begin // int -> double
// correctly sign extend the integer depending on if it's a signed/unsigned test // correctly sign extend the integer depending on if it's a signed/unsigned test
X = {P.FLEN{1'bx}}; X = {P.Q_LEN{1'bx}};
SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]}; SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]};
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
end end
2'b01: begin // double -> long 2'b01: begin // double -> long
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
end end
2'b00: begin // double -> int 2'b00: begin // double -> int
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; Ans = {{P.Q_LEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
end end
endcase endcase
end end
@ -1321,25 +1325,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
// {is the integer a long, is the opperation to an integer} // {is the integer a long, is the opperation to an integer}
casez ({OpCtrl[2:1]}) casez ({OpCtrl[2:1]})
2'b11: begin // long -> single 2'b11: begin // long -> single
X = {P.FLEN{1'bx}}; X = {P.Q_LEN{1'bx}};
SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)]; SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b10: begin // int -> single 2'b10: begin // int -> single
// correctly sign extend the integer depending on if it's a signed/unsigned test // correctly sign extend the integer depending on if it's a signed/unsigned test
X = {P.FLEN{1'bx}}; X = {P.Q_LEN{1'bx}};
SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]}; SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]};
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
end end
2'b01: begin // single -> long 2'b01: begin // single -> long
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
end end
2'b00: begin // single -> int 2'b00: begin // single -> int
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]};
end end
endcase endcase
end end
@ -1347,25 +1351,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
// {is the integer a long, is the opperation to an integer} // {is the integer a long, is the opperation to an integer}
casez ({OpCtrl[2:1]}) casez ({OpCtrl[2:1]})
2'b11: begin // long -> half 2'b11: begin // long -> half
X = {P.FLEN{1'bx}}; X = {P.Q_LEN{1'bx}};
SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)]; SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
2'b10: begin // int -> half 2'b10: begin // int -> half
// correctly sign extend the integer depending on if it's a signed/unsigned test // correctly sign extend the integer depending on if it's a signed/unsigned test
X = {P.FLEN{1'bx}}; X = {P.Q_LEN{1'bx}};
SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]}; SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]};
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
end end
2'b01: begin // half -> long 2'b01: begin // half -> long
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
end end
2'b00: begin // half -> int 2'b00: begin // half -> int
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
SrcA = {P.XLEN{1'bx}}; SrcA = {P.XLEN{1'bx}};
Ans = {{P.FLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
end end
endcase endcase
end end

7
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md
View File

@ -22,7 +22,12 @@ riscv-ctg-> This folder consists of the CTG tool which is responsible for genera
riscof -> The riscof directory in Wally was changed to include some Quad precision template files for compilation. Along with modification of scripts and yaml files to support FLEN=128 riscof -> The riscof directory in Wally was changed to include some Quad precision template files for compilation. Along with modification of scripts and yaml files to support FLEN=128
TO DO:
Debug why fadd.q_b1 doesn't match Sail vs. Spike
Run the q test on Wally RTL
Make more tests from the working datasets
Get other datasets working by using softfloat to do quad math
Push changes back to riscv-ctg and riscv-isac and remove them from wally-riscv-arch/tsts/riscv-test-suite/rv64i_m/Q
Start by installing riscv-ctg via the following commands : Start by installing riscv-ctg via the following commands :