diff --git a/bin/regression-wally b/bin/regression-wally index 0e641dceb..ed725b51a 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -313,8 +313,8 @@ os.chdir(regressionDir) coveragesim = "questa" # Questa is required for code/functional coverage #defaultsim = "vcs" # Default simulator for all other tests; change to Verilator when flow is ready -defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready -#defaultsim = "verilator" # Default simulator for all other tests +#defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready +defaultsim = "verilator" # Default simulator for all other tests coverage = '--coverage' in sys.argv fp = '--fp' in sys.argv @@ -323,9 +323,8 @@ testfloat = '--testfloat' in sys.argv if (nightly): nightMode = "--nightly"; -# sims = [defaultsim] - sims = ["questa", "vcs"] -# sims = ["questa", "verilator", "vcs"] # *** uncomment to exercise all simulators +# sims = [defaultsim] # uncomment to use only the default simulator + sims = ["questa", "verilator", "vcs"] # uncomment to exercise all simulators else: nightMode = "" sims = [defaultsim] @@ -352,6 +351,7 @@ if (coverage): # only run RV64GC tests on Questa in coverage mode addTests(tests64gc_fp, "questa") else: for sim in sims: + addTests(tests_buildrootshort, sim) addTests(tests, sim) addTests(tests64gc_nofp, sim) addTests(tests64gc_fp, sim) @@ -359,10 +359,7 @@ else: # run derivative configurations in nightly regression if (nightly): # addTests(tests_buildrootboot, defaultsim) - addTests(tests_buildrootshort, defaultsim) addTests(derivconfigtests, defaultsim) -else: - addTests(tests_buildrootshort, defaultsim) # testfloat tests if (testfloat): # for testfloat alone, just run testfloat tests @@ -433,9 +430,10 @@ def main(): """Run the tests and count the failures""" global configs, coverage os.chdir(regressionDir) - os.system('rm -rf questa/wkdir') - for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]: + dirs = ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"] + for d in dirs: try: + os.system('rm -rf %s' % d) os.mkdir(d) except: pass diff --git a/bin/wsim b/bin/wsim index 9884992e4..35b48dbb1 100755 --- a/bin/wsim +++ b/bin/wsim @@ -14,38 +14,16 @@ import argparse import os -def LaunchSim(ElfFile): - # Launch selected simulator + +def LaunchSim(ElfFile, flags): cd = "cd $WALLY/sim/" +args.sim - # ugh. can't have more than 9 arguments passed to vsim. why? I'll have to remove --lockstep when running - # functional coverage and imply it. + + # per-simulator launch if (args.sim == "questa"): - if (args.lockstep): - prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic" - if(int(args.locksteplog) >= 1): EnableLog = 1 - else: EnableLog = 0 - if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) - else: ImperasPlusArgs = "" - if(args.fcov): - CovEnableStr = "1" if int(args.covlog) > 0 else "0"; - if(args.covlog >= 1): EnableLog = 1 - else: EnableLog = 0 - ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr; - suffix = "" - else: - CovEnableStr = "" - suffix = "--lockstep" - else: - prefix = "" - ImperasPlusArgs = "" - suffix = "" + # Questa cannot accept more than 9 arguments. fcov implies lockstep if (args.tb == "testbench_fp"): args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args - cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + suffix + " " + ImperasPlusArgs - if (args.coverage): - cmd += " --coverage" - if (args.fcov): - cmd += " --fcov" + cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + flags if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible if(args.tb == "testbench"): cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc -GDEBUG=1\"" @@ -58,24 +36,20 @@ def LaunchSim(ElfFile): elif (args.sim == "verilator"): # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i print(f"Running Verilator on {args.config} {args.testsuite}") - if (args.coverage): - print("Coverage option not available for Verilator") - exit(1) - if (args.gui): - print("GUI option not available for Verilator") - exit(1) os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} EXTRA_ARGS='{args.args}'") elif (args.sim == "vcs"): print(f"Running VCS on " + args.config + " " + args.testsuite) if (args.gui): args.args += "gui" - elif (args.coverage): - args.args += "coverage" - cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.args + cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.args + " " + flags print(cmd) os.system(cmd) +######################## +# main wsim script +######################## + # Parse arguments parser = argparse.ArgumentParser() parser.add_argument("config", help="Configuration file") @@ -96,6 +70,7 @@ print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim ElfFile="" DirectorMode = 0 ElfList = [] +WALLY = os.environ.get('WALLY') if(os.path.isfile(args.testsuite)): ElfFile = "+ElfFile=" + args.testsuite @@ -111,21 +86,43 @@ elif(os.path.isdir(args.testsuite)): print(ElfList) # Validate arguments -if (args.gui): +if (args.gui or args.coverage or args.fcov or args.lockstep): if args.sim not in ["questa", "vcs"]: - print("GUI option only supported for Questa and VCS") - exit(1) - -if (args.coverage): - if args.sim not in ["questa", "vcs"]: - print("Coverage option only available for Questa and VCS") + print("Option only supported for Questa and VCS") exit(1) if (args.vcd): args.args += " -DMAKEVCD=1" +# if lockstep is enabled, then we need to pass the Imperas lockstep arguments +if(int(args.locksteplog) >= 1): EnableLog = 1 +else: EnableLog = 0 +if (args.lockstep): + prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic" + if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) + else: ImperasPlusArgs = "" + if(args.fcov): + CovEnableStr = "1" if int(args.covlog) > 0 else "0"; + if(args.covlog >= 1): EnableLog = 1 + else: EnableLog = 0 + ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr; + suffix = "" + else: + CovEnableStr = "" + suffix = "--lockstep" +else: + prefix = "" + ImperasPlusArgs = "" + suffix = "" +flags = suffix + " " + ImperasPlusArgs + +# other flags +if (args.coverage): + flags += " --coverage" +if (args.fcov): + flags += " --fcov" + # create the output sub-directories. -WALLY = os.environ.get('WALLY') regressionDir = WALLY + '/sim/' for d in ["logs", "wkdir", "cov"]: try: @@ -135,7 +132,7 @@ for d in ["logs", "wkdir", "cov"]: if(DirectorMode): for ElfFile in ElfList: - LaunchSim(ElfFile) + LaunchSim(ElfFile, flags) else: - LaunchSim(ElfFile) + LaunchSim(ElfFile, flags) diff --git a/config/derivlist.txt b/config/derivlist.txt index 48f69e7cf..7bd878aaf 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -814,11 +814,13 @@ deriv f_rv32gc rv32gc D_SUPPORTED 0 ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 +ZCD_SUPPORTED 0 deriv fh_rv32gc rv32gc D_SUPPORTED 0 ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 +ZCD_SUPPORTED 0 deriv fd_rv32gc rv32gc ZFH_SUPPORTED 0 @@ -838,11 +840,13 @@ deriv f_rv64gc rv64gc D_SUPPORTED 0 ZCD_SUPPORTED 0 ZFH_SUPPORTED 0 +ZCD_SUPPORTED 0 deriv fh_rv64gc rv64gc D_SUPPORTED 0 ZCD_SUPPORTED 0 ZFH_SUPPORTED 1 +ZCD_SUPPORTED 0 deriv fd_rv64gc rv64gc ZFH_SUPPORTED 0 diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 80385f6ba..e5ef6456e 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -90,29 +90,28 @@ RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/ # Simulation and Coverage Commands OUTPUT="sim_out" -VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn ${INCLUDE_PATH} $RTL_FILES" -SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS}" -COV_FILES="${TB}/coverage/test_pmp_coverage.sv" -COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE" -### CODE COVERAGE REPORT in IndividualCovReport in XML format -#COV_RUN="urg -dir ${WKDIR}/COVERAGE.vdb -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}" -### CODE COVERAGE REPORT in IndividualCovReport in text format -COV_RUN="urg -dir ./${WKDIR}/COVERAGE.vdb -format text -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}" - +VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn ${INCLUDE_PATH} " # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson +SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS} -no_save" # Clean and run simulation with VCS -if [ "$3" = "coverage" ]; then +if [ "$3" = "--coverage" ]; then echo -e "${YELLOW}#### Running VCS Simulation with Coverage ####${NC}" - # Code Coverage. - $VCS_CMD -Mdir=${WKDIR} $COV_OPTIONS -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log" - $SIMV_CMD $COV_OPTIONS + COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE" + COV_RUN="urg -dir ./${WKDIR}/COVERAGE.vdb -format text -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}" + $VCS_CMD -Mdir=${WKDIR} $COV_OPTIONS $RTL_FILES -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log" + $SIMV_CMD $COV_OPTIONS # dh 6/27/24 *** are COV_OPTIONS really needed? $COV_RUN #cp -rf urgReport $COV - +elif [ "$3" = "--lockstep" ]; then + echo -e "${YELLOW}#### Running VCS Simulation with Lockstep ####${NC}" + LOCKSTEP_OPTIONS=" +define+USE_IMPERAS_DV +incdir+${IMPERAS_HOME}/ImpPublic/include/host +incdir+${IMPERAS_HOME}/ImpProprietary/include/host ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv ${TB}/common/wallyTracer.sv" + LOCKSTEP_SIMV="-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model" + $VCS_CMD -Mdir=${WKDIR} $LOCKSTEP_OPTIONS $RTL_FILES -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log" + $SIMV_CMD $LOCKSTEP_SIMV else echo -e "${YELLOW}#### Running VCS Simulation ####${NC}" - $VCS_CMD -Mdir=${WKDIR} -o ${WKDIR}/$OUTPUT -work ${WKDIR} -Mlib ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log" + $VCS_CMD -Mdir=${WKDIR} $RTL_FILES -o ${WKDIR}/$OUTPUT -work ${WKDIR} -Mlib ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log" $SIMV_CMD fi diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index 7287e6962..5479e0deb 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -66,6 +66,7 @@ module testbench_fp; logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit + logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags logic [4:0] CmpFlg; // Outputed flags logic AnsNaN, ResNaN, NaNGood; @@ -820,13 +821,14 @@ module testbench_fp; end always_comb begin + FpResExtended = {{(P.Q_LEN-P.FLEN){1'b1}}, FpRes}; // select the result to check case (UnitVal) - `FMAUNIT: Res = FpRes; - `DIVUNIT: Res = FpRes; - `CMPUNIT: Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, CmpRes}; - `CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, IntRes}; else Res = FpRes; - `CVTFPUNIT: Res = FpRes; + `FMAUNIT: Res = FpResExtended; + `DIVUNIT: Res = FpResExtended; + `CMPUNIT: Res = {{(Q_LEN-XLEN){1'b0}}, CmpRes}; + `CVTINTUNIT: if (WriteIntVal) Res = {{(Q_LEN-XLEN){1'b0}}, IntRes}; else Res = FpResExtended; + `CVTFPUNIT: Res = FpResExtended; endcase // select the flag to check @@ -965,7 +967,7 @@ module testbench_fp; /////////////////////////////////////////////////////////////////////////////////////////////// // check if result is correct - assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx)); + assign ResMatch = ((Res[P.FLEN-1:0] === Ans[P.FLEN-1:0]) | NaNGood | (NaNGood === 1'bx)); assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx)); assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL); assign FMAop = (OpCtrlVal == `FMAUNIT); @@ -987,7 +989,7 @@ module testbench_fp; // increment the test TestNum += 1; // clear the vectors - for(int i=0; i quad - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)]; Ans = TestVector[8+(P.Q_LEN-1):8]; end 2'b10: begin // int -> quad // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]}; Ans = TestVector[8+(P.Q_LEN-1):8]; end 2'b01: begin // quad -> long X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; end 2'b00: begin // quad -> int X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end @@ -1295,25 +1299,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( // {Int->Fp?, is the integer a long} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> double - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)]; - Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; + Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b10: begin // int -> double // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]}; - Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; + Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]}; end 2'b01: begin // double -> long - X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; + X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; end 2'b00: begin // double -> int - X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; + X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{P.Q_LEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end @@ -1321,25 +1325,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( // {is the integer a long, is the opperation to an integer} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> single - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)]; - Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; + Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b10: begin // int -> single // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]}; - Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; + Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]}; end 2'b01: begin // single -> long - X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; + X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; end 2'b00: begin // single -> int - X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; + X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]}; end endcase end @@ -1347,25 +1351,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( // {is the integer a long, is the opperation to an integer} casez ({OpCtrl[2:1]}) 2'b11: begin // long -> half - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)]; - Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; + Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end 2'b10: begin // int -> half // correctly sign extend the integer depending on if it's a signed/unsigned test - X = {P.FLEN{1'bx}}; + X = {P.Q_LEN{1'bx}}; SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]}; - Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; + Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]}; end 2'b01: begin // half -> long - X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; + X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]}; end 2'b00: begin // half -> int - X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; + X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{P.FLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; + Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; end endcase end diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md index c624e624b..bee5c000d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md @@ -22,7 +22,12 @@ riscv-ctg-> This folder consists of the CTG tool which is responsible for genera riscof -> The riscof directory in Wally was changed to include some Quad precision template files for compilation. Along with modification of scripts and yaml files to support FLEN=128 - +TO DO: + Debug why fadd.q_b1 doesn't match Sail vs. Spike + Run the q test on Wally RTL + Make more tests from the working datasets + Get other datasets working by using softfloat to do quad math + Push changes back to riscv-ctg and riscv-isac and remove them from wally-riscv-arch/tsts/riscv-test-suite/rv64i_m/Q Start by installing riscv-ctg via the following commands :