mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'dev' into installation
This commit is contained in:
Jordan Carlin
commit
045bdddfde
@ -313,8 +313,8 @@ os.chdir(regressionDir)
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coveragesim = "questa" # Questa is required for code/functional coverage
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#defaultsim = "vcs" # Default simulator for all other tests; change to Verilator when flow is ready
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defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
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#defaultsim = "verilator" # Default simulator for all other tests
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#defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
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defaultsim = "verilator" # Default simulator for all other tests
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coverage = '--coverage' in sys.argv
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fp = '--fp' in sys.argv
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@ -323,9 +323,8 @@ testfloat = '--testfloat' in sys.argv
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if (nightly):
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nightMode = "--nightly";
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# sims = [defaultsim]
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sims = ["questa", "vcs"]
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# sims = ["questa", "verilator", "vcs"] # *** uncomment to exercise all simulators
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# sims = [defaultsim] # uncomment to use only the default simulator
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sims = ["questa", "verilator", "vcs"] # uncomment to exercise all simulators
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else:
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nightMode = ""
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sims = [defaultsim]
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@ -352,6 +351,7 @@ if (coverage): # only run RV64GC tests on Questa in coverage mode
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addTests(tests64gc_fp, "questa")
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else:
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for sim in sims:
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addTests(tests_buildrootshort, sim)
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addTests(tests, sim)
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addTests(tests64gc_nofp, sim)
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addTests(tests64gc_fp, sim)
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@ -359,10 +359,7 @@ else:
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# run derivative configurations in nightly regression
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if (nightly):
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# addTests(tests_buildrootboot, defaultsim)
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addTests(tests_buildrootshort, defaultsim)
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addTests(derivconfigtests, defaultsim)
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else:
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addTests(tests_buildrootshort, defaultsim)
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# testfloat tests
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if (testfloat): # for testfloat alone, just run testfloat tests
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@ -433,9 +430,10 @@ def main():
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"""Run the tests and count the failures"""
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global configs, coverage
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os.chdir(regressionDir)
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os.system('rm -rf questa/wkdir')
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for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]:
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dirs = ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]
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for d in dirs:
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try:
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os.system('rm -rf %s' % d)
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os.mkdir(d)
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except:
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pass
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91
bin/wsim
91
bin/wsim
@ -14,38 +14,16 @@
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import argparse
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import os
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def LaunchSim(ElfFile):
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# Launch selected simulator
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def LaunchSim(ElfFile, flags):
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cd = "cd $WALLY/sim/" +args.sim
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# ugh. can't have more than 9 arguments passed to vsim. why? I'll have to remove --lockstep when running
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# functional coverage and imply it.
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# per-simulator launch
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if (args.sim == "questa"):
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if (args.lockstep):
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prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic"
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if(int(args.locksteplog) >= 1): EnableLog = 1
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else: EnableLog = 0
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if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
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else: ImperasPlusArgs = ""
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if(args.fcov):
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CovEnableStr = "1" if int(args.covlog) > 0 else "0";
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if(args.covlog >= 1): EnableLog = 1
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else: EnableLog = 0
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ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr;
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suffix = ""
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else:
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CovEnableStr = ""
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suffix = "--lockstep"
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else:
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prefix = ""
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ImperasPlusArgs = ""
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suffix = ""
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# Questa cannot accept more than 9 arguments. fcov implies lockstep
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if (args.tb == "testbench_fp"):
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args.args = " -GTEST=\"" + args.testsuite + "\" " + args.args
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cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + suffix + " " + ImperasPlusArgs
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if (args.coverage):
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cmd += " --coverage"
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if (args.fcov):
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cmd += " --fcov"
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cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args + " " + ElfFile + " " + flags
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if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
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if(args.tb == "testbench"):
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cmd = cd + "; " + prefix + " vsim -do \"" + cmd + " +acc -GDEBUG=1\""
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@ -58,24 +36,20 @@ def LaunchSim(ElfFile):
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elif (args.sim == "verilator"):
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# PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i
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print(f"Running Verilator on {args.config} {args.testsuite}")
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if (args.coverage):
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print("Coverage option not available for Verilator")
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exit(1)
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if (args.gui):
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print("GUI option not available for Verilator")
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exit(1)
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os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite} TESTBENCH={args.tb} EXTRA_ARGS='{args.args}'")
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elif (args.sim == "vcs"):
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print(f"Running VCS on " + args.config + " " + args.testsuite)
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if (args.gui):
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args.args += "gui"
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elif (args.coverage):
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args.args += "coverage"
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cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.args
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cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.args + " " + flags
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print(cmd)
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os.system(cmd)
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########################
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# main wsim script
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########################
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# Parse arguments
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parser = argparse.ArgumentParser()
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parser.add_argument("config", help="Configuration file")
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@ -96,6 +70,7 @@ print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim
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ElfFile=""
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DirectorMode = 0
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ElfList = []
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WALLY = os.environ.get('WALLY')
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if(os.path.isfile(args.testsuite)):
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ElfFile = "+ElfFile=" + args.testsuite
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@ -111,21 +86,43 @@ elif(os.path.isdir(args.testsuite)):
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print(ElfList)
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# Validate arguments
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if (args.gui):
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if (args.gui or args.coverage or args.fcov or args.lockstep):
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if args.sim not in ["questa", "vcs"]:
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print("GUI option only supported for Questa and VCS")
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exit(1)
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if (args.coverage):
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if args.sim not in ["questa", "vcs"]:
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print("Coverage option only available for Questa and VCS")
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print("Option only supported for Questa and VCS")
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exit(1)
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if (args.vcd):
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args.args += " -DMAKEVCD=1"
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# if lockstep is enabled, then we need to pass the Imperas lockstep arguments
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if(int(args.locksteplog) >= 1): EnableLog = 1
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else: EnableLog = 0
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if (args.lockstep):
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prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic"
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if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
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else: ImperasPlusArgs = ""
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if(args.fcov):
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CovEnableStr = "1" if int(args.covlog) > 0 else "0";
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if(args.covlog >= 1): EnableLog = 1
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else: EnableLog = 0
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ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr;
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suffix = ""
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else:
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CovEnableStr = ""
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suffix = "--lockstep"
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else:
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prefix = ""
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ImperasPlusArgs = ""
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suffix = ""
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flags = suffix + " " + ImperasPlusArgs
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# other flags
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if (args.coverage):
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flags += " --coverage"
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if (args.fcov):
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flags += " --fcov"
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# create the output sub-directories.
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WALLY = os.environ.get('WALLY')
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regressionDir = WALLY + '/sim/'
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for d in ["logs", "wkdir", "cov"]:
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try:
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@ -135,7 +132,7 @@ for d in ["logs", "wkdir", "cov"]:
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if(DirectorMode):
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for ElfFile in ElfList:
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LaunchSim(ElfFile)
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LaunchSim(ElfFile, flags)
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else:
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LaunchSim(ElfFile)
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LaunchSim(ElfFile, flags)
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@ -814,11 +814,13 @@ deriv f_rv32gc rv32gc
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D_SUPPORTED 0
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ZCD_SUPPORTED 0
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ZFH_SUPPORTED 0
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ZCD_SUPPORTED 0
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deriv fh_rv32gc rv32gc
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D_SUPPORTED 0
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ZCD_SUPPORTED 0
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ZFH_SUPPORTED 1
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ZCD_SUPPORTED 0
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deriv fd_rv32gc rv32gc
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ZFH_SUPPORTED 0
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@ -838,11 +840,13 @@ deriv f_rv64gc rv64gc
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D_SUPPORTED 0
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ZCD_SUPPORTED 0
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ZFH_SUPPORTED 0
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ZCD_SUPPORTED 0
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deriv fh_rv64gc rv64gc
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D_SUPPORTED 0
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ZCD_SUPPORTED 0
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ZFH_SUPPORTED 1
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ZCD_SUPPORTED 0
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deriv fd_rv64gc rv64gc
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ZFH_SUPPORTED 0
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@ -90,29 +90,28 @@ RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/
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# Simulation and Coverage Commands
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OUTPUT="sim_out"
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VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn ${INCLUDE_PATH} $RTL_FILES"
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SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS}"
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COV_FILES="${TB}/coverage/test_pmp_coverage.sv"
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COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE"
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### CODE COVERAGE REPORT in IndividualCovReport in XML format
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#COV_RUN="urg -dir ${WKDIR}/COVERAGE.vdb -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}"
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### CODE COVERAGE REPORT in IndividualCovReport in text format
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COV_RUN="urg -dir ./${WKDIR}/COVERAGE.vdb -format text -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}"
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VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn ${INCLUDE_PATH} " # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson
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SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS} -no_save"
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# Clean and run simulation with VCS
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if [ "$3" = "coverage" ]; then
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if [ "$3" = "--coverage" ]; then
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echo -e "${YELLOW}#### Running VCS Simulation with Coverage ####${NC}"
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# Code Coverage.
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$VCS_CMD -Mdir=${WKDIR} $COV_OPTIONS -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
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$SIMV_CMD $COV_OPTIONS
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COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE"
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COV_RUN="urg -dir ./${WKDIR}/COVERAGE.vdb -format text -report IndividualCovReport/${CONFIG_VARIANT}_${TESTSUITE}"
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$VCS_CMD -Mdir=${WKDIR} $COV_OPTIONS $RTL_FILES -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
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$SIMV_CMD $COV_OPTIONS # dh 6/27/24 *** are COV_OPTIONS really needed?
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$COV_RUN
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#cp -rf urgReport $COV
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|
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elif [ "$3" = "--lockstep" ]; then
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echo -e "${YELLOW}#### Running VCS Simulation with Lockstep ####${NC}"
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LOCKSTEP_OPTIONS=" +define+USE_IMPERAS_DV +incdir+${IMPERAS_HOME}/ImpPublic/include/host +incdir+${IMPERAS_HOME}/ImpProprietary/include/host ${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv ${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv ${TB}/common/wallyTracer.sv"
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LOCKSTEP_SIMV="-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model"
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$VCS_CMD -Mdir=${WKDIR} $LOCKSTEP_OPTIONS $RTL_FILES -o ${WKDIR}/$OUTPUT -Mlib ${WKDIR} -work ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
|
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$SIMV_CMD $LOCKSTEP_SIMV
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else
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echo -e "${YELLOW}#### Running VCS Simulation ####${NC}"
|
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$VCS_CMD -Mdir=${WKDIR} -o ${WKDIR}/$OUTPUT -work ${WKDIR} -Mlib ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
|
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$VCS_CMD -Mdir=${WKDIR} $RTL_FILES -o ${WKDIR}/$OUTPUT -work ${WKDIR} -Mlib ${WKDIR} -l "$LOGS/${CONFIG_VARIANT}_${TESTSUITE}.log"
|
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$SIMV_CMD
|
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fi
|
||||
|
||||
|
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@ -66,6 +66,7 @@ module testbench_fp;
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logic [P.FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad
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logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
|
||||
logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit
|
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logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res
|
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logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags
|
||||
logic [4:0] CmpFlg; // Outputed flags
|
||||
logic AnsNaN, ResNaN, NaNGood;
|
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@ -820,13 +821,14 @@ module testbench_fp;
|
||||
end
|
||||
|
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always_comb begin
|
||||
FpResExtended = {{(P.Q_LEN-P.FLEN){1'b1}}, FpRes};
|
||||
// select the result to check
|
||||
case (UnitVal)
|
||||
`FMAUNIT: Res = FpRes;
|
||||
`DIVUNIT: Res = FpRes;
|
||||
`CMPUNIT: Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, CmpRes};
|
||||
`CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, IntRes}; else Res = FpRes;
|
||||
`CVTFPUNIT: Res = FpRes;
|
||||
`FMAUNIT: Res = FpResExtended;
|
||||
`DIVUNIT: Res = FpResExtended;
|
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`CMPUNIT: Res = {{(Q_LEN-XLEN){1'b0}}, CmpRes};
|
||||
`CVTINTUNIT: if (WriteIntVal) Res = {{(Q_LEN-XLEN){1'b0}}, IntRes}; else Res = FpResExtended;
|
||||
`CVTFPUNIT: Res = FpResExtended;
|
||||
endcase
|
||||
|
||||
// select the flag to check
|
||||
@ -965,7 +967,7 @@ module testbench_fp;
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// check if result is correct
|
||||
assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
|
||||
assign ResMatch = ((Res[P.FLEN-1:0] === Ans[P.FLEN-1:0]) | NaNGood | (NaNGood === 1'bx));
|
||||
assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
|
||||
assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
|
||||
assign FMAop = (OpCtrlVal == `FMAUNIT);
|
||||
@ -987,7 +989,7 @@ module testbench_fp;
|
||||
// increment the test
|
||||
TestNum += 1;
|
||||
// clear the vectors
|
||||
for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}};
|
||||
for(int i=0; i<MAXVECTORS; i++) TestVectors[i] = {P.Q_LEN*4+8{1'bx}};
|
||||
// read next files
|
||||
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
|
||||
// set the vector index back to 0
|
||||
@ -1052,6 +1054,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
// Format of vectors Inputs(1/2/3)_AnsFlg
|
||||
always @(VectorNum) begin
|
||||
AnsFlg = TestVector[4:0];
|
||||
//$display("Entering readvectors with VectorNum=%d, TestVector=%x, Unit=%d, Fmt=%d, OpCtrl=%d", VectorNum, TestVector, Unit, Fmt, OpCtrl);
|
||||
case (Unit)
|
||||
`FMAUNIT:
|
||||
case (Fmt)
|
||||
@ -1070,48 +1073,49 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
if (OpCtrl === `FMA_OPCTRL) begin
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]};
|
||||
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
|
||||
Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]};
|
||||
Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
|
||||
Z = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]};
|
||||
$display("Read %x %x %x", X, Y, Z);
|
||||
end
|
||||
else begin
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
|
||||
if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
else Y = {{P.FLEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)};
|
||||
if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}};
|
||||
else Z = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
|
||||
if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
else Y = {{P.Q_LEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)};
|
||||
if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.D_LEN{1'b1}}, {P.D_LEN{1'b0}}};
|
||||
else Z = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
end
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: if (P.F_SUPPORTED) begin // single
|
||||
if (OpCtrl === `FMA_OPCTRL) begin
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]};
|
||||
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
|
||||
Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]};
|
||||
Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
|
||||
Z = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]};
|
||||
end
|
||||
else begin
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
|
||||
if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
|
||||
else Y = {{P.FLEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)};
|
||||
if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}};
|
||||
else Z = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
|
||||
if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
|
||||
else Y = {{P.Q_LEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)};
|
||||
if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.S_LEN{1'b1}}, {P.S_LEN{1'b0}}};
|
||||
else Z = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
|
||||
end
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
if (OpCtrl === `FMA_OPCTRL) begin
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]};
|
||||
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]};
|
||||
Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
Z = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]};
|
||||
end
|
||||
else begin
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
if (OpCtrl === `MUL_OPCTRL) Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
else Y = {{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)};
|
||||
if (OpCtrl === `MUL_OPCTRL) Z = {{P.FLEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}};
|
||||
else Z = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
else Y = {{P.Q_LEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)};
|
||||
if (OpCtrl === `MUL_OPCTRL) Z = {{P.Q_LEN-P.H_LEN{1'b1}}, {P.H_LEN{1'b0}}};
|
||||
else Z = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
end
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
`DIVUNIT:
|
||||
@ -1122,16 +1126,16 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: if (P.F_SUPPORTED) begin // single
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
else
|
||||
@ -1142,19 +1146,19 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
|
||||
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
|
||||
Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: if (P.F_SUPPORTED) begin // single
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
|
||||
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
|
||||
Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
|
||||
Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
`CMPUNIT:
|
||||
@ -1162,22 +1166,22 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
2'b11: begin // quad
|
||||
X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)];
|
||||
Y = TestVector[12+(P.Q_LEN)-1:12];
|
||||
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
|
||||
Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
|
||||
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
|
||||
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
|
||||
Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
|
||||
Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
|
||||
end
|
||||
2'b00: if (P.F_SUPPORTED) begin // single
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
|
||||
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
|
||||
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
|
||||
Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
|
||||
Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
|
||||
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
|
||||
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
|
||||
Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
|
||||
Ans = {{P.Q_LEN-1{1'b0}}, TestVector[8]};
|
||||
end
|
||||
endcase
|
||||
`CVTFPUNIT:
|
||||
@ -1190,75 +1194,75 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {TestVector[8+P.Q_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: begin // single
|
||||
X = {TestVector[8+P.Q_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
X = {TestVector[8+P.Q_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
case (OpCtrl[1:0])
|
||||
2'b11: begin // quad
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: begin // double
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: begin // single
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.D_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b00: if (P.F_SUPPORTED) begin // single
|
||||
case (OpCtrl[1:0])
|
||||
2'b11: begin // quad
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: begin // single
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.S_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b10: begin // half
|
||||
case (OpCtrl[1:0])
|
||||
2'b11: begin // quad
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.Q_LEN-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.D_LEN-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b00: if (P.F_SUPPORTED) begin // single
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.S_LEN-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.H_LEN+P.H_LEN-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@ -1269,25 +1273,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casez ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> quad
|
||||
X = {P.FLEN{1'bx}};
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b10: begin // int -> quad
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.FLEN{1'bx}};
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.Q_LEN+32-1]}}, TestVector[8+P.Q_LEN+32-1:8+(P.Q_LEN)]};
|
||||
Ans = TestVector[8+(P.Q_LEN-1):8];
|
||||
end
|
||||
2'b01: begin // quad -> long
|
||||
X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||
Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
|
||||
end
|
||||
2'b00: begin // quad -> int
|
||||
X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@ -1295,25 +1299,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
// {Int->Fp?, is the integer a long}
|
||||
casez ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> double
|
||||
X = {P.FLEN{1'bx}};
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> double
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.FLEN{1'bx}};
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.D_LEN+32-1]}}, TestVector[8+P.D_LEN+32-1:8+(P.D_LEN)]};
|
||||
Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // double -> long
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||
Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
|
||||
end
|
||||
2'b00: begin // double -> int
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
|
||||
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
Ans = {{P.Q_LEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@ -1321,25 +1325,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casez ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> single
|
||||
X = {P.FLEN{1'bx}};
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> single
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.FLEN{1'bx}};
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.S_LEN+32-1]}}, TestVector[8+P.S_LEN+32-1:8+(P.S_LEN)]};
|
||||
Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // single -> long
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||
Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
|
||||
end
|
||||
2'b00: begin // single -> int
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
|
||||
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
@ -1347,25 +1351,25 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casez ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> half
|
||||
X = {P.FLEN{1'bx}};
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
2'b10: begin // int -> half
|
||||
// correctly sign extend the integer depending on if it's a signed/unsigned test
|
||||
X = {P.FLEN{1'bx}};
|
||||
X = {P.Q_LEN{1'bx}};
|
||||
SrcA = {{P.XLEN-32{TestVector[8+P.H_LEN+32-1]}}, TestVector[8+P.H_LEN+32-1:8+(P.H_LEN)]};
|
||||
Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
Ans = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
|
||||
end
|
||||
2'b01: begin // half -> long
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||
Ans = {{(P.Q_LEN-64){1'b0}}, TestVector[8+(64-1):8]};
|
||||
end
|
||||
2'b00: begin // half -> int
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
|
||||
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.FLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
|
||||
Ans = {{(P.Q_LEN-32){TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
@ -22,7 +22,12 @@ riscv-ctg-> This folder consists of the CTG tool which is responsible for genera
|
||||
|
||||
riscof -> The riscof directory in Wally was changed to include some Quad precision template files for compilation. Along with modification of scripts and yaml files to support FLEN=128
|
||||
|
||||
|
||||
TO DO:
|
||||
Debug why fadd.q_b1 doesn't match Sail vs. Spike
|
||||
Run the q test on Wally RTL
|
||||
Make more tests from the working datasets
|
||||
Get other datasets working by using softfloat to do quad math
|
||||
Push changes back to riscv-ctg and riscv-isac and remove them from wally-riscv-arch/tsts/riscv-test-suite/rv64i_m/Q
|
||||
|
||||
|
||||
Start by installing riscv-ctg via the following commands :
|
||||
|
||||
Loading…
Reference in New Issue
Block a user