diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 843efdd62..ddf0f77dc 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -253,7 +253,10 @@ module lsu (
 
   if(`DMEM != `MEM_BUS) begin // *** always, not just with no MEM_BUS.  Only produces byte write enable
     logic [`XLEN-1:0] ReadDataWordMaskedM;
+    // ** there is definitely a sww bug with memory mapped i/o. check wally64priv.    
     assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate
+    // *** consider moving this AND gate into the sww.
+    //assign ReadDataWordMaskedM = ReadDataWordM; // *** this change only works because the i/o devices dont' write bytes other than the ones specific to their address.
     subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]),
       .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
          .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM));