From 0222e8f42add640fd8f5d16bc32bf6d6890dec68 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Mon, 4 Mar 2024 17:52:41 -0600
Subject: [PATCH] Don't want to clear the lru bits on invalidation
 (clearvalid).

---
 src/cache/cacheLRU.sv | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 2670af93f..71b11abee 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -144,9 +144,7 @@ module cacheLRU
   always_ff @(posedge clk) begin
     if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; // exclusion-tag: initialize
     if(CacheEn) begin
-      if(ClearValid & ~FlushStage)
-        LRUMemory[PAdr] <= '0;
-      else if(LRUWriteEn)
+      if(LRUWriteEn)
         LRUMemory[PAdr] <= NextLRU;
       if(LRUWriteEn & (PAdr == CacheSetTag))
         CurrLRU <= #1 NextLRU;