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Fixed K extension changes

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This commit is contained in:
KelvinTr 2024-02-28 17:05:08 -06:00
parent 0d4d996655
commit 01c45ab9d7
30 changed files with 298 additions and 178 deletions
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14
config/rv32gc/config.vh
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@ -181,13 +181,13 @@ localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// K extension instructions
localparam ZBKB_SUPPORTED = 0;
localparam ZBKC_SUPPORTED = 0;
localparam ZBKX_SUPPORTED = 0;
localparam ZKNE_SUPPORTED = 0;
localparam ZKND_SUPPORTED = 0;
localparam ZK_SUPPORTED = 0;
localparam ZKNH_SUPPORTED = 0;
localparam ZBKB_SUPPORTED = 1;
localparam ZBKC_SUPPORTED = 1;
localparam ZBKX_SUPPORTED = 1;
localparam ZKND_SUPPORTED = 1;
localparam ZKNE_SUPPORTED = 1;
localparam ZKNH_SUPPORTED = 1;
localparam ZK_SUPPORTED = 1;
// Memory synthesis configuration
localparam USE_SRAM = 0;

14
config/rv64gc/config.vh
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@ -182,13 +182,13 @@ localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// K extension instructions
localparam ZBKB_SUPPORTED = 0;
localparam ZBKC_SUPPORTED = 0;
localparam ZBKX_SUPPORTED = 0;
localparam ZKNE_SUPPORTED = 0;
localparam ZKND_SUPPORTED = 0;
localparam ZK_SUPPORTED = 0;
localparam ZKNH_SUPPORTED = 0;
localparam ZBKB_SUPPORTED = 1;
localparam ZBKC_SUPPORTED = 1;
localparam ZBKX_SUPPORTED = 1;
localparam ZKND_SUPPORTED = 1;
localparam ZKNE_SUPPORTED = 1;
localparam ZKNH_SUPPORTED = 1;
localparam ZK_SUPPORTED = 1;
// Memory synthesis configuration
localparam USE_SRAM = 0;

1
config/shared/config-shared.vh
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@ -29,6 +29,7 @@ localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);
localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1);
localparam K_SUPPORTED = ((ZBKB_SUPPORTED | ZBKC_SUPPORTED | ZBKX_SUPPORTED | ZKND_SUPPORTED | ZKNE_SUPPORTED | ZKNH_SUPPORTED));
localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1);
localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1);
localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1);

8
config/shared/parameter-defs.vh
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@ -113,6 +113,13 @@ localparam cvw_t P = '{
ZCB_SUPPORTED : ZCB_SUPPORTED,
ZCD_SUPPORTED : ZCD_SUPPORTED,
ZCF_SUPPORTED : ZCF_SUPPORTED,
ZBKB_SUPPORTED: ZBKB_SUPPORTED,
ZBKC_SUPPORTED: ZBKC_SUPPORTED,
ZBKX_SUPPORTED: ZBKX_SUPPORTED,
ZKND_SUPPORTED: ZKND_SUPPORTED,
ZKNE_SUPPORTED: ZKNE_SUPPORTED,
ZKNH_SUPPORTED: ZKNH_SUPPORTED,
ZK_SUPPORTED : ZK_SUPPORTED,
USE_SRAM : USE_SRAM,
M_MODE : M_MODE,
S_MODE : S_MODE,
@ -136,6 +143,7 @@ localparam cvw_t P = '{
E_SUPPORTED : E_SUPPORTED,
F_SUPPORTED : F_SUPPORTED,
I_SUPPORTED : I_SUPPORTED,
K_SUPPORTED : K_SUPPORTED,
M_SUPPORTED : M_SUPPORTED,
Q_SUPPORTED : Q_SUPPORTED,
S_SUPPORTED : S_SUPPORTED,

4
sim/regression-wally
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@ -88,7 +88,7 @@ for test in tests64i:
configs.append(tc)
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zbc", "arch32zfad",
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad",
#tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"]
for test in tests32gc:
tc = TestCase(
@ -127,7 +127,7 @@ for test in tests32e:
grepstr="All tests ran without failures")
configs.append(tc)
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad",
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working
#tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
# "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"]

4
src/cvw.sv
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@ -187,8 +187,7 @@ typedef struct packed {
logic ZKND_SUPPORTED;
logic ZKNE_SUPPORTED;
logic ZKNH_SUPPORTED;
logic ZKSED_SUPPORTED;
logic ZKSH_SUPPORTED;
logic ZK_SUPPORTED;
// Memory synthesis configuration
logic USE_SRAM;
@ -224,6 +223,7 @@ typedef struct packed {
logic E_SUPPORTED;
logic F_SUPPORTED;
logic I_SUPPORTED;
logic K_SUPPORTED;
logic M_SUPPORTED;
logic Q_SUPPORTED;
logic S_SUPPORTED;

47
src/ieu/aes_common/aes_inv_shiftrow.sv
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@ -28,32 +28,39 @@
module aes_Inv_shiftrow(input logic [127:0] DataIn,
output logic [127:0] DataOut);
logic [7:0] w0_b0, w0_b1, w0_b2, w0_b3;
logic [7:0] w1_b0, w1_b1, w1_b2, w1_b3;
logic [7:0] w2_b0, w2_b1, w2_b2, w2_b3;
logic [7:0] w3_b0, w3_b1, w3_b2, w3_b3;
logic [31:0] out_w0, out_w1, out_w2, out_w3;
// Separate the first (Least Significant) word into bytes
logic [7:0] w0_b0 = DataIn[7:0];
logic [7:0] w0_b1 = DataIn[15:8];
logic [7:0] w0_b2 = DataIn[23:16];
logic [7:0] w0_b3 = DataIn[31:24];
assign w0_b0 = DataIn[7:0];
assign w0_b1 = DataIn[15:8];
assign w0_b2 = DataIn[23:16];
assign w0_b3 = DataIn[31:24];
// Separate the second word into bytes
logic [7:0] w1_b0 = DataIn[39:32];
logic [7:0] w1_b1 = DataIn[47:40];
logic [7:0] w1_b2 = DataIn[55:48];
logic [7:0] w1_b3 = DataIn[63:56];
assign w1_b0 = DataIn[39:32];
assign w1_b1 = DataIn[47:40];
assign w1_b2 = DataIn[55:48];
assign w1_b3 = DataIn[63:56];
// Separate the third word into bytes
logic [7:0] w2_b0 = DataIn[71:64];
logic [7:0] w2_b1 = DataIn[79:72];
logic [7:0] w2_b2 = DataIn[87:80];
logic [7:0] w2_b3 = DataIn[95:88];
assign w2_b0 = DataIn[71:64];
assign w2_b1 = DataIn[79:72];
assign w2_b2 = DataIn[87:80];
assign w2_b3 = DataIn[95:88];
// Separate the fourth (Most significant) word into bytes
logic [7:0] w3_b0 = DataIn[103:96];
logic [7:0] w3_b1 = DataIn[111:104];
logic [7:0] w3_b2 = DataIn[119:112];
logic [7:0] w3_b3 = DataIn[127:120];
assign w3_b0 = DataIn[103:96];
assign w3_b1 = DataIn[111:104];
assign w3_b2 = DataIn[119:112];
assign w3_b3 = DataIn[127:120];
// The output words are composed of sets of the input bytes.
logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
assign out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
assign out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
assign out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
assign out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
assign DataOut = {out_w0, out_w1, out_w2, out_w3};
endmodule

46
src/ieu/aes_common/aes_shiftrow.sv
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@ -31,31 +31,37 @@ module aes_shiftrow(input logic [127:0] DataIn,
// (This form of writing it may seem like more effort but I feel
// like it is more self-explanatory this way without losing efficiency)
logic [7:0] w0_b0, w0_b1, w0_b2, w0_b3;
logic [7:0] w1_b0, w1_b1, w1_b2, w1_b3;
logic [7:0] w2_b0, w2_b1, w2_b2, w2_b3;
logic [7:0] w3_b0, w3_b1, w3_b2, w3_b3;
logic [31:0] out_w0, out_w1, out_w2, out_w3;
// Seperate the first (Least Significant) word into bytes
logic [7:0] w0_b0 = DataIn[7:0];
logic [7:0] w0_b1 = DataIn[79:72];
logic [7:0] w0_b2 = DataIn[23:16];
logic [7:0] w0_b3 = DataIn[95:88];
assign w0_b0 = DataIn[7:0];
assign w0_b1 = DataIn[79:72];
assign w0_b2 = DataIn[23:16];
assign w0_b3 = DataIn[95:88];
// Seperate the second word into bytes
logic [7:0] w1_b0 = DataIn[39:32];
logic [7:0] w1_b1 = DataIn[111:104];
logic [7:0] w1_b2 = DataIn[55:48];
logic [7:0] w1_b3 = DataIn[127:120];
assign w1_b0 = DataIn[39:32];
assign w1_b1 = DataIn[111:104];
assign w1_b2 = DataIn[55:48];
assign w1_b3 = DataIn[127:120];
// Seperate the third word into bytes
logic [7:0] w2_b0 = DataIn[71:64];
logic [7:0] w2_b1 = DataIn[15:8];
logic [7:0] w2_b2 = DataIn[87:80];
logic [7:0] w2_b3 = DataIn[31:24];
assign w2_b0 = DataIn[71:64];
assign w2_b1 = DataIn[15:8];
assign w2_b2 = DataIn[87:80];
assign w2_b3 = DataIn[31:24];
// Seperate the fourth (Most significant) word into bytes
logic [7:0] w3_b0 = DataIn[103:96];
logic [7:0] w3_b1 = DataIn[47:40];
logic [7:0] w3_b2 = DataIn[119:112];
logic [7:0] w3_b3 = DataIn[63:56];
assign w3_b0 = DataIn[103:96];
assign w3_b1 = DataIn[47:40];
assign w3_b2 = DataIn[119:112];
assign w3_b3 = DataIn[63:56];
// The output words are composed of sets of the input bytes.
logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
assign out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
assign out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
assign out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
assign out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
assign DataOut = {out_w0, out_w1, out_w2, out_w3};

5
src/ieu/aes_instructions/aes32dsi.sv
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@ -46,13 +46,14 @@ module aes32dsi(input logic [1:0] bs,
assign Sbox_In = Sbox_In_32[7:0];
// Apply inverse sbox to si
aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
aes_Inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
// Pad output of inverse substitution box
assign so = {24'h0, Sbox_Out};
// Rotate the substitution box output left by shamt (bs * 8)
rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate));
// rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate));
assign so_rotate = (so << shamt) | (so >> (32 - shamt));
// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
assign Data_Out = rs1 ^ so_rotate;

5
src/ieu/aes_instructions/aes32dsmi.sv
View File

@ -47,7 +47,7 @@ module aes32dsmi(input logic [1:0] bs,
assign Sbox_In = Sbox_In_32[7:0];
// Apply inverse sbox to si
aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
aes_Inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
// Pad output of inverse substitution box
assign so = {24'h0, Sbox_Out};
@ -56,7 +56,8 @@ module aes32dsmi(input logic [1:0] bs,
inv_mixword mix(.word(so), .mixed_word(mixed));
// Rotate the substitution box output left by shamt (bs * 8)
rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate));
// rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate));
assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt));
// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
assign Data_Out = rs1 ^ mixed_rotate;

3
src/ieu/aes_instructions/aes32esi.sv
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@ -54,7 +54,8 @@ module aes32esi(input logic [1:0] bs,
assign so = {24'h0, Sbox_Out};
// Rotate so left by shamt
rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate));
// rotate_left rol32(.input_data(so), .shamt(shamt), .rot_data(so_rotate));
assign so_rotate = (so << shamt) | (so >> (32 - shamt));
// Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt));
assign Data_Out = rs1 ^ so_rotate;

3
src/ieu/aes_instructions/aes32esmi.sv
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@ -58,7 +58,8 @@ module aes32esmi(input logic [1:0] bs,
mixword mwd(.word(so), .mixed_word(mixed));
// Rotate so left by shamt
rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate));
// rotate_left rol32(.input_data(mixed), .shamt(shamt), .rot_data(mixed_rotate));
assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt));
// Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt));
assign Data_Out = rs1 ^ mixed_rotate;

6
src/ieu/aes_instructions/aes64ds.sv
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@ -35,11 +35,11 @@ module aes64ds(input logic [63:0] rs1,
logic [31:0] Sbox_Out_1;
// Apply inverse shiftrows to rs2 and rs1
aes_inv_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out));
aes_Inv_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
// Apply full word inverse substitution to lower 2 words of shiftrow out
aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
aes_Inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
aes_Inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
// Concatenate the two substitution outputs to get result
assign Data_Out = {Sbox_Out_1, Sbox_Out_0};

6
src/ieu/aes_instructions/aes64dsm.sv
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@ -37,11 +37,11 @@ module aes64dsm(input logic [63:0] rs1,
logic [31:0] Mixcol_Out_1;
// Apply inverse shiftrows to rs2 and rs1
aes_inv_shiftrow srow(.dataIn({rs2, rs1}), .dataOut(ShiftRow_Out));
aes_Inv_shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out));
// Apply full word inverse substitution to lower 2 words of shiftrow out
aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
aes_Inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
aes_Inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
// Apply inverse mixword to sbox outputs
inv_mixword inv_mw_0(.word(Sbox_Out_0), .mixed_word(Mixcol_Out_0));

2
src/ieu/aes_instructions/aes64es.sv
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@ -33,7 +33,7 @@ module aes64es(input logic [63:0] rs1,
logic [127:0] ShiftRow_Out;
// AES shiftrow unit
aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out));
aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
// Apply substitution box to 2 lower words
aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0]));

2
src/ieu/aes_instructions/aes64esm.sv
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@ -34,7 +34,7 @@ module aes64esm(input logic [63:0] rs1,
logic [63:0] Sbox_Out;
// AES shiftrow unit
aes_shiftrow srow(.dataIn({rs2,rs1}), .dataOut(ShiftRow_Out));
aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
// Apply substitution box to 2 lower words
aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0]));

60
src/ieu/aes_instructions/aes64ks1i.sv
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@ -58,63 +58,3 @@ module aes64ks1i(input logic [3:0] roundnum,
endmodule
module rcon_lut_128(input logic [3:0] RD,
output logic [7:0] rcon_out);
always_comb
begin
case(RD)
4'h0 : rcon_out = 8'h01;
4'h1 : rcon_out = 8'h02;
4'h2 : rcon_out = 8'h04;
4'h3 : rcon_out = 8'h08;
4'h4 : rcon_out = 8'h10;
4'h5 : rcon_out = 8'h20;
4'h6 : rcon_out = 8'h40;
4'h7 : rcon_out = 8'h80;
4'h8 : rcon_out = 8'h1b;
4'h9 : rcon_out = 8'h36;
4'hA : rcon_out = 8'h00;
default : rcon_out = 8'h00;
endcase
end
endmodule
module rrot8(input logic[31:0] x,
output logic [31:0] result);
assign result[0] = x[8];
assign result[1] = x[9];
assign result[2] = x[10];
assign result[3] = x[11];
assign result[4] = x[12];
assign result[5] = x[13];
assign result[6] = x[14];
assign result[7] = x[15];
assign result[8] = x[16];
assign result[9] = x[17];
assign result[10] = x[18];
assign result[11] = x[19];
assign result[12] = x[20];
assign result[13] = x[21];
assign result[14] = x[22];
assign result[15] = x[23];
assign result[16] = x[24];
assign result[17] = x[25];
assign result[18] = x[26];
assign result[19] = x[27];
assign result[20] = x[28];
assign result[21] = x[29];
assign result[22] = x[30];
assign result[23] = x[31];
assign result[24] = x[0];
assign result[25] = x[1];
assign result[26] = x[2];
assign result[27] = x[3];
assign result[28] = x[4];
assign result[29] = x[5];
assign result[30] = x[6];
assign result[31] = x[7];
endmodule

14
src/ieu/kmu/packer.sv
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@ -37,7 +37,6 @@ module packer #(parameter WIDTH=32) (
logic [WIDTH-1:0] Pack;
logic [WIDTH-1:0] PackH;
logic [WIDTH-1:0] PackW;
logic [1:0] MuxSelect;
assign low_half = A[WIDTH/2-1:0];
assign high_half = B[WIDTH/2-1:0];
@ -50,18 +49,11 @@ module packer #(parameter WIDTH=32) (
assign PackH = {{(WIDTH-16){1'b0}}, high_halfh, low_halfh};
assign PackW = {{(WIDTH-32){high_halfw[15]}}, high_halfw, low_halfw};
// TODO: FIX THIS ... this is completely incorrect way to use if statements
// Solution for now:
always_comb
begin
if (PackSelect[1:0] == 2'b11)
MuxSelect = 2'b01;
else if (PackSelect[2] == 1'b0)
MuxSelect = 2'b00;
else
MuxSelect = 2'b10;
if (PackSelect[1:0] == 2'b11) PackResult = PackH;
else if (PackSelect[2] == 1'b0) PackResult = Pack;
else PackResult = PackW;
end
mux3 #(WIDTH) PackMux(Pack, PackH, PackW, MuxSelect, PackResult);
endmodule

4
src/ieu/kmu/zknd_32.sv
View File

@ -36,8 +36,8 @@ module zknd_32 #(parameter WIDTH=32)
logic [31:0] aes32dsmiRes;
// RV32
aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32dsiRes));
aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32dsmiRes));
aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32dsiRes));
aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32dsmiRes));
mux2 #(WIDTH) zkndmux (aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult);

6
src/ieu/kmu/zknd_64.sv
View File

@ -40,9 +40,9 @@ module zknd_64 #(parameter WIDTH=32)
logic [63:0] aes64ks2Res;
// RV64
aes64ds aes64ds (.rs1(A), .rs2(B), .data_out(aes64dsRes));
aes64dsm aes64dsm (.rs1(A), .rs2(B), .data_out(aes64dsmRes));
aes64im aes64im (.rs1(A), .data_out(aes64imRes));
aes64ds aes64ds (.rs1(A), .rs2(B), .Data_Out(aes64dsRes));
aes64dsm aes64dsm (.rs1(A), .rs2(B), .Data_Out(aes64dsmRes));
aes64im aes64im (.rs1(A), .Data_Out(aes64imRes));
aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));

4
src/ieu/kmu/zkne_32.sv
View File

@ -36,8 +36,8 @@ module zkne_32 #(parameter WIDTH=32)
logic [31:0] aes32esmiRes;
// RV32
aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32esiRes));
aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .data_out(aes32esmiRes));
aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32esiRes));
aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .Data_Out(aes32esmiRes));
mux2 #(WIDTH) zknemux (aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult);

4
src/ieu/kmu/zkne_64.sv
View File

@ -39,8 +39,8 @@ module zkne_64 #(parameter WIDTH=32)
logic [63:0] aes64ks2Res;
// RV64
aes64es aes64es (.rs1(A), .rs2(B), .data_out(aes64esRes));
aes64esm aes64esm (.rs1(A), .rs2(B), .data_out(aes64esmRes));
aes64es aes64es (.rs1(A), .rs2(B), .Data_Out(aes64esRes));
aes64esm aes64esm (.rs1(A), .rs2(B), .Data_Out(aes64esmRes));
aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));

32
testbench/common/instrNameDecTB.sv
View File

@ -58,6 +58,17 @@ module instrNameDecTB(
else if (funct7[6:1] == 6'b010010) name = "BCLRI";
else if (funct7[6:1] == 6'b011010) name = "BINVI";
else if (funct7[6:1] == 6'b001010) name = "BSETI";
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP";
else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM";
else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I";
else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1";
else if (funct7 == 7'b0110000) begin
case (rs2)
5'b00000: name = "CLZ";
@ -77,6 +88,8 @@ module instrNameDecTB(
else if (funct7[6:1] == 6'b011000) name = "RORI";
else if (funct7[6:1] == 6'b010010) name = "BEXTI";
else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
else if (imm == 12'b011010000111) name = "BREV8";
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP";
else name = "ILLEGAL";
10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I";
else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
@ -130,6 +143,21 @@ module instrNameDecTB(
10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
else if (funct7 == 7'b0000001) name = "MUL";
else if (funct7 == 7'b0100000) name = "SUB";
else if (funct7[4:0] == 5'b10101) name = "AES32DSI";
else if (funct7[4:0] == 5'b10111) name = "AES32DSMI";
else if (funct7 == 7'b0011101) name = "AES64DS";
else if (funct7 == 7'b0011111) name = "AES64DSM";
else if (funct7[4:0] == 5'b10001) name = "AES32ESI";
else if (funct7[4:0] == 5'b10011) name = "AES32ESMI";
else if (funct7 == 7'b0011001) name = "AES64ES";
else if (funct7 == 7'b0011011) name = "AES64ESM";
else if (funct7 == 7'b0111111) name = "AES64KS2";
else if (funct7 == 7'b0101110) name = "SHA512SIG0H";
else if (funct7 == 7'b0101010) name = "SHA512SIG0L";
else if (funct7 == 7'b0101111) name = "SHA512SIG1H";
else if (funct7 == 7'b0101011) name = "SHA512SIG1L";
else if (funct7 == 7'b0101000) name = "SHA512SUM0R";
else if (funct7 == 7'b0101001) name = "SHA512SUM1R";
else name = "ILLEGAL";
10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
else if (funct7 == 7'b0000001) name = "MULH";
@ -153,7 +181,9 @@ module instrNameDecTB(
else if (funct7 == 7'b0010000) name = "SH2ADD";
else if (funct7 == 7'b0000101) name = "MIN";
else if (funct7 == 7'b0100000) name = "ORN";
else if (funct7 == 7'b0000100) name = "ZEXT.H";
else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H";
else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK";
else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW";
else name = "ILLEGAL";
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
else if (funct7 == 7'b0000001) name = "DIVU";

12
testbench/testbench-xcelium.sv
View File

@ -129,6 +129,12 @@ module testbench;
"arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb;
"arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc;
"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
"arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb;
"arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc;
"arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx;
"arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd;
"arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne;
"arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh;
endcase
end else begin // RV32
case (TEST)
@ -159,6 +165,12 @@ module testbench;
"arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb;
"arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc;
"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
"arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb;
"arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc;
"arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx;
"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
endcase
end
if (tests.size() == 0) begin

12
testbench/testbench.sv
View File

@ -147,6 +147,12 @@ module testbench;
"arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf;
"arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad;
"buildroot": tests = buildroot;
"arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb;
"arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc;
"arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx;
"arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd;
"arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne;
"arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh;
endcase
end else begin // RV32
case (TEST)
@ -189,6 +195,12 @@ module testbench;
"arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt;
"arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf;
"arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad;
"arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb;
"arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc;
"arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx;
"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
endcase
end
if (tests.size() == 0) begin

96
testbench/tests.vh
View File

@ -990,6 +990,53 @@ string imperas32f[] = '{
"rv32i_m/B/src/bseti-01.S"
};
string arch32zbkb[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/brev8_32-01.S",
"rv32i_m/K/src/pack-01.S",
"rv32i_m/K/src/packh-01.S",
"rv32i_m/K/src/unzip-01.S",
"rv32i_m/K/src/zip-01.S"
};
string arch32zbkc[] = '{
`RISCVARCHTEST,
"rv32i_m/B/src/clmul-01.S",
"rv32i_m/B/src/clmulh-01.S"
};
string arch32zbkx[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/xperm8-01.S",
"rv32i_m/K/src/xperm4-01.S"
};
string arch32zknd[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/aes32dsi-01.S",
"rv32i_m/K/src/aes32dsmi-01.S"
};
string arch32zkne[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/aes32esi-01.S",
"rv32i_m/K/src/aes32esmi-01.S"
};
string arch32zknh[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/sha256sig0-01.S",
"rv32i_m/K/src/sha256sig1-01.S",
"rv32i_m/K/src/sha256sum0-01.S",
"rv32i_m/K/src/sha256sum1-01.S",
"rv32i_m/K/src/sha512sig0h-01.S",
"rv32i_m/K/src/sha512sig0l-01.S",
"rv32i_m/K/src/sha512sig1h-01.S",
"rv32i_m/K/src/sha512sig1l-01.S",
"rv32i_m/K/src/sha512sum0r-01.S",
"rv32i_m/K/src/sha512sum1r-01.S"
};
string arch64m[] = '{
`RISCVARCHTEST,
"rv64i_m/M/src/div-01.S",
@ -1748,6 +1795,55 @@ string arch64zbs[] = '{
"rv64i_m/B/src/bseti-01.S"
};
string arch64zbkb[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/brev8-01.S",
"rv64i_m/K/src/pack-01.S",
"rv64i_m/K/src/packh-01.S",
"rv64i_m/K/src/packw-01.S"
};
string arch64zbkc[] = '{
`RISCVARCHTEST,
"rv64i_m/B/src/clmul-01.S",
"rv64i_m/B/src/clmulh-01.S"
};
string arch64zbkx[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/xperm8-01.S",
"rv64i_m/K/src/xperm4-01.S"
};
string arch64zknd[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/aes64ds-01.S",
"rv64i_m/K/src/aes64dsm-01.S",
"rv64i_m/K/src/aes64im-01.S",
"rv64i_m/K/src/aes64ks1i-01.S",
"rv64i_m/K/src/aes64ks2-01.S"
};
string arch64zkne[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/aes64es-01.S",
"rv64i_m/K/src/aes64esm-01.S",
"rv64i_m/K/src/aes64ks1i-01.S",
"rv64i_m/K/src/aes64ks2-01.S"
};
string arch64zknh[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/sha256sig0-01.S",
"rv64i_m/K/src/sha256sig1-01.S",
"rv64i_m/K/src/sha256sum0-01.S",
"rv64i_m/K/src/sha256sum1-01.S",
"rv64i_m/K/src/sha512sig0-01.S",
"rv64i_m/K/src/sha512sig1-01.S",
"rv64i_m/K/src/sha512sum0-01.S",
"rv64i_m/K/src/sha512sum1-01.S"
};
string arch32priv[] = '{
`RISCVARCHTEST,
"rv32i_m/privilege/src/ebreak.S",

12
tests/riscof/spike/riscof_spike.py
View File

@ -131,6 +131,18 @@ class spike(pluginTemplate):
self.isa += '_Zbc'
if "Zbs" in ispec["ISA"]:
self.isa += '_Zbs'
if "Zbkb" in ispec["ISA"]:
self.isa += '_Zbkb'
if "Zbkc" in ispec["ISA"]:
self.isa += '_Zbkc'
if "Zknd" in ispec["ISA"]:
self.isa += '_Zknd'
if "Zkne" in ispec["ISA"]:
self.isa += '_Zkne'
if "Zbkx" in ispec["ISA"]:
self.isa += '_Zbkx'
if "Zknh" in ispec["ISA"]:
self.isa += '_Zknh'
#TODO: The following assumes you are using the riscv-gcc toolchain. If
# not please change appropriately

2
tests/riscof/spike/spike_rv32e_isa.yaml
View File

@ -1,6 +1,6 @@
hart_ids: [0]
hart0:
ISA: RV32EMCZicsr_Zifencei
ISA: RV32EMCZicsr_Zifencei_Zbkc
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]